EE 410 / Saraswat Handout #3 - Stanford Nanofabrication Facility

EE410 / Saraswat Handout #3
o Remove the wavers and run “POLYPUMP”.
• The target poly thickness is ~500 nm.
• This step takes ~3 hrs of tube time.
13. PM #3 Polisilicon (STEPS 3.000-3.190)
Poly Thickness (STEP 2.420):
The Nanospec can measure semi-transparent films (thin poly), but requires the underlying oxide
thickness. In this case examine the poly over the active cuts and enter the measured gate oxide
thickness.
• Make sure that the Nano-spec is focused on a poly region not covered by resist.
• Measure the poly thickness on T, using the Nano-spec, the poly on oxide program, and the
10X objective.
• Use F-6 (poly on gate oxide) on the selected wafer dies.
• Measure 5 points on the wafer (flat down, toward you) and record the results below and on
the runsheet:
Top_______________
Left _________________ Center _____________ Right _______________
Bottom _____________
Photomask #3 Polysilicon Lithography
This step delineates the gates. It is important that the lithography be performed with care to keep
the gates the correct lengths. Also, examine that the gate/active overlap is sufficient.
The litho process steps are:
• Singe & Prime in the yes
• Spin coat using svgcoat/2 programs 9 (no prime), 7 (1.0 µm of 3612 resist w/2 mm EBR),
and 1 (prebake 90 C for 60").
• Expose on the asml
Job name: EE410R_1
Layer ID: 3
Layer Number: POLY
Image ID: POLY
Reticle ID: EE410RET2
• Post-exposure bake on svgdev/2 using programs 9 (no develop) and 1 (post-expose
bake@110º C for 60").
• Resist develop on svgdev using programs 3 (develop) and 1 (postbake@110º C for 60")
• Inspect. Check the alignment Verniers and record the alignment offsets. You should be
able to align to within 0.5 µm from the ACTIVE level.
• Rework as necessary.
Vernier #31: POLY to ACTIVE (offset: ____ / ____ )
Revised Jan. 11, 2008 Page 22/47