EE 410 / Saraswat Handout #3 - Stanford Nanofabrication Facility
EE 410 / Saraswat Handout #3 - Stanford Nanofabrication Facility
EE 410 / Saraswat Handout #3 - Stanford Nanofabrication Facility
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<strong>EE</strong><strong>410</strong> / <strong>Saraswat</strong> <strong>Handout</strong> <strong>#3</strong><br />
SECTION 1 - Runsheet Revisions<br />
This process has been developed with the help of many people, most without attribution. This<br />
section is intended to set that straight, and keep a log of changes. As things are changed, add<br />
them to this list!<br />
• This process was developed by Alvin Loke in ’94, with some parts based on an earlier process.<br />
• Field oxide etch modified from dry etch to wet. This provides better step control and avoids<br />
plasma damage to active silicon.<br />
• 1998 Vivek Subramanian, Celisa Date: Metal thickness increased from 0.5 to 1.0 microns for<br />
better step coverage. Resist hardening for n+ select reduced to ease strip.<br />
• 1999 Aaron Partridge, with input from Jitendra Mohan, Ken Honer and Bart Kane: Deep well<br />
implant energy reduced from 200KeV to 180keV because the implanter is not reliable at 200KeV.<br />
Gate oxide regrown just prior to poly deposition for clean gates. Gate reoxidation concatenated<br />
with poly dep to minimize gate exposure. Poly etch changed from isotropic to vertical because<br />
stringers are not a problem with wet FOX etch, and steep sidewalls improve gate length control.<br />
Resist hardening bake on n+ select reduced form 180C to 110C to avoid reticulation. LTO<br />
deposition and reflow concatenated to avoid reentrant steps. This document expanded in various<br />
descriptions.<br />
• 2000, 2001 Aaron Partridge, Pranav Kalavade: N++ implant dropped from 180KeV to 100KeV for<br />
easier outside implants. N++ drive added to push arsenic. Resist spin and development updated<br />
to new resist and programs. Resist descum added prior to active etch for good wetting. Resist<br />
stripper updated. LTO drive switched from inner to wet. Other small updates.<br />
• 2002 Nabeel Ibrahim, Steve Jurichich, and Jim McVittie: Al/Si Etch changed from Wet to Dry Etch.<br />
Schedule modified (by Chi On Chui and Nabeel Ibrahim) to distribute processing more evenly<br />
throughout the quarter. Additional cleans and postbakes added as necessary because of modified<br />
schedule. Change N++ implant back to 180KeV from 100KeV as implants will be done in-house,<br />
drop drive-in step.<br />
• 2003 Chi On Chui, Rohit Shoney: New Ultratech reticles (<strong>EE</strong><strong>410</strong>A_03 & <strong>EE</strong><strong>410</strong>B_03) made with<br />
new Vernier mark sets added. The PAD level removed. Two new fields added for contact metal<br />
liftoff (METAL_LO) and SOI/LOCOS isolation (ACTIVE_R), respectively. N++ implant dropped<br />
again from 180KeV to ??KeV for easier outside implants. N++ drive-in revoked to push arsenic.<br />
Both the runsheet and instruction manual updated.<br />
• 2006 Dawson Wong: Replaced Standard, Matrix, and PRX-127 resist strips with Gasonics.<br />
Deleted silicon etch after contact hole etch. Deleted plasma freckle etch after metal etch.<br />
Furnaces use N2 ambient instead of Ar. Increased resist thickness for Photolithography #6 to 1.6<br />
um. Updated conditions for implants, poly etch and contact hole etch. Updated Tylan tube<br />
numbers.<br />
• 2007 SNF Process Staff: Transferred from Ultratech stepper to ASML. Transferred to "Clean"<br />
equipment. Defined "Standard" cleans. Updated process descriptions in this document.<br />
Developed <strong>EE</strong><strong>410</strong> industry-style runcard that travels with the wafers as they are processed.<br />
Revised Jan. 11, 2008 Page 2/47
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