EE 410 / Saraswat Handout #3 - Stanford Nanofabrication Facility

EE410 / Saraswat Handout #3
• Measure the field oxide thickness on T, using the Nanospec, the thick oxide program, and
the 10X objective.
• Use the region marked F-1 on the selected wafer die.
• Measure 5 points on the wafer (flat down, toward you) and record the results below and on
the runsheet:
Top_______________
Left _________________ Center _____________ Right _______________
Bottom _____________
Sacrificial Oxide Thickness:
Since we do not have a chance to measure the gate oxide thickness (because we don’t want to
handle it!) we measure the sacrificial oxide thickness now. This oxide is just like the gate oxide,
and the thickness should be quite similar.
• Measure the sacrificial oxide thickness on T, using the Nano-spec, the thin oxide program,
and the 10X objective.
• Use the region marked F-2 on the selected wafer dies.
• Measure 5 points on the wafer (flat down, toward you) and record the results below and on
the runsheet:
Top_______________
Left _________________ Center _____________ Right _______________
Bottom _____________
9. PM #2: P-Well (STEPS 2.000-2.190)
This is the second alignment step. Note: This is a dark field mask (i.e., one that is mostly opaque)
which tends to be more difficult to align than a clear field mask.
The litho process steps are:
• Singe & Prime in the yes
• Spin coat using svgcoat/2 programs 9 (no prime), 7 (1.0 µm of 3612 resist w/2 mm EBR),
and 1 (prebake 90 C for 60").
• Expose on the asml
Job name: EE410R_1
Layer ID: 2
Layer Number: PWELL
Image ID: PWELL
Reticle ID: EE410RET1
• Post-exposure bake on svgdev/2 using programs 9 (no develop) and 1 (post-expose
bake@110º C for 60").
• Resist develop on svgdev using programs 3 (develop) and 1 (postbake@110º C for 60")
Revised Jan. 11, 2008 Page 19/47