EE 410 / Saraswat Handout #3 - Stanford Nanofabrication Facility
EE 410 / Saraswat Handout #3 - Stanford Nanofabrication Facility
EE 410 / Saraswat Handout #3 - Stanford Nanofabrication Facility
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<strong>EE</strong><strong>410</strong> / <strong>Saraswat</strong> <strong>Handout</strong> <strong>#3</strong><br />
3D. <strong>EE</strong><strong>410</strong> Device Test Structure Layout<br />
Alvin Loke designed a set of test structures for ee<strong>410</strong>. There is more here than we have time to test, but<br />
if something goes wrong there is enough to find the problem.<br />
• On each die, six groups of test structures will be fabricated:<br />
1. Fabrication test structures (F series),<br />
2. Process test structures (P series),<br />
3. Device test structures (D series),<br />
4. Circuit test structures (C series),<br />
5. SEM test structures, and<br />
6. Vernier alignment test structures.<br />
• These test structures are approximately fabricated in the following arrangement.<br />
Revised Jan. 11, 2008 Page 13/47
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