AN4603 - Freescale Semiconductor

Freescale Semiconductor 

Application Note 

1 Purpose 

The present document is intended to teach the reader how to 

supply the power management to the i.MX50x family of 

processors using either the Freescale MC13892 or the 

MC34709 as the main power management device. 

2 Introduction 

The i.MX50x family of microprocessors requires complex 

power management distribution along with specific 

sequencing for proper power up. To supply integrated power 

management to the i.MX50 processors, Freescale provides 

two highly integrated PMICs solutions for different specific 

scenarios. The MC13892, provide a highly integrated solution 

which provides most of the required voltage rails as well as 

integrated battery charger, 10 bits ADC and backlight LED 

drivers. Likewise, the MC34709 is a reduced solution 

providing as well the majority of the required power rails for 

applications with less system requirements. 

© Freescale Semiconductor, Inc., 2012. All rights reserved. 

 

Document Number: AN4603 

Rev. 1.0, 12/2012 

Power Management Design Guidelines for 

the i.MX50x Family of Microprocessors 

Contents 

1 Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 

2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1 

3 i.MX50 Microprocessor Overview . . . . . . . . 2 

4 i.MX50 Power Management Design with 

MC13892 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 

5 i.MX50 Power Management Design with the 

MC34709 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 

6 References . . . . . . . . . . . . . . . . . . . . . . . . . . 43 

7 Revision History . . . . . . . . . . . . . . . . . . . . . 44

i.MX50 Microprocessor Overview 

3 i.MX50 Microprocessor Overview 

The i.MX50 Applications Processors (i.MX50) is part of a growing family of multimedia-focused products, offering 

high performance processing optimized for lowest power consumption. 

The i.MX50 is optimized for portable multimedia applications and it features Freescale's advanced implementation 

of the ARM Cortex-A8 core, which operates at speed as high as 800 MHz. The i.MX50 provides a powerful display 

architecture, including a 2D Graphics Processing Unit (GPU) and Pixel Processing Pipeline (ePXP). In addition, 

i.MX508 includes a complete integration of the electrophoretic display function. The i.MX50 supports DDR2, 

LPDDR2, and LPDDR1 DRAM at clock rate up to 266 MHz to enable a range of performance and power trade-offs. 

The flexibility of the i.MX50 architecture allows it to be used in a variety of applications. As the heart of the application 

chipset, the i.MX50 provides a rich set of interfaces for connecting peripherals, such as WLAN, Bluetooth, GPS, 

and displays. 

i.MX50 power requirements are summarized in Table 1. 

Table 1. i.MX50 Power requirements 

Voltage Domain Voltage Current 

Name Description TYP Units Max Units 

VDDGP 400< fARM ≤ 800 MHz 1.05 V 1250 mA 

167< fARM ≤ 400 MHz 0.95 V 

24< fARM ≤ 167 MHz 0.9 V 

Stop Mode 0.85 V 

VCC LPM 0.95 V 400 mA 

RPM 1.05 V 

HPM 1.225 V 

VDDA Run Mode 1.2 V 250 mA 


VDDAL1 Run Mode 1.2 V 


VDD3P0 Bandgap and 480 MHz PLL 

supply 

VDD2P5 Efuse, 24 MHz oscillator, 32 kHz 

oscillator mux supply 

3.0 V 10 mA 

2.5 V 150 mA 

VDD1P2 PLL digital supplies 1.8 V 10 mA 

VDD1P8 PLL analog supplies 1.8 V 10 mA 

NVCC_JTAG GPIO digital power supplies 1.875 or 2.775 V 

NVCC_EMI_DRAM DDR2/LPDDR1 1.8 V 350 mA 

LPDDR2 1.2 V 

Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 

2 Freescale Semiconductor

VREF DRAM Reference Voltage Input 1/2 

NVCC_E 

MI_DRAM 

i.MX50 Microprocessor Overview 

V 0.004 mA 

VDDO25 EMI Pad Predriver supply 2.5 V 10 mA 

NVCC_NANDF 

NVCC_SD1 

NVCC_SD2 

NVCC_KEYPAD 

NVCC_EIM 

NVCC_EPDC 

NVCC_LCD 

NVCC_MISC 

NVCC_SPI 

NVCC_SSI 

NVCC_UART 

High voltage I/O (HVIO) 

supplies 

NVCC_SRTC SRTC core and I/O supply 

(LVIO) 

HVIO_L=1.875 

HVIO_H=3.0 


Freescale Semiconductor 3 

V 

1.2 V 

NVCC_RESET LVIO 1.875 or 2.775 V 

USB_H1_VDDA25 

USB_OTG_VDDA25 

USB_DDA33 

USB_OTG_VDA33 

Table 1. i.MX50 Power requirements 

Voltage Domain Voltage Current 

Name Description TYP Units Max Units 

USB_PHY analog supply 2.5 V 50 mA 

USB PHY I/O analog supply 3.3 V 16 mA

i.MX50 Power Management Design with MC13892 

3.1 i.MX50 Power-up/down Sequence 

VDDGP 

VDDA 

VDDAL1 

Figure 1. i.MX50 Power up Sequence 

NOTE 

• The POR_B input must be immediately asserted at power-up and remain 

asserted until after the last power rail is at its working voltage. 

• No power-up sequence dependencies exist between the supplies shown 

shaded in gray. 

3.2 Power-Down Sequence 

NVCC_SRTC 

The power-down sequence is recommended to be the opposite of the power-up sequence. In other words, the same 

power supply constraints exist while powering off as while powering on. 

4 i.MX50 Power Management Design with MC13892 

VCC 

VDD3P0 VDDO2P5 

VDD2P5 

VDD1P8 VDD1P2 

NVCC_EMI_DRAM 

VREF 

NVCC_EIM 

NVCC_EPDC 

NVCC_JTAG 

NVCC_KEYPAD 

NVCC_LCD 

NVCC_MISC 

NVCC_NANDF 

NVCC_RESET 

NVCC_SD1 

NVCC_SD2 

NVCC_SSI 

NVCC_UART 


USB_H1_VDDA25 


USB_H1_VDDA33 

The MC13892 is a power management IC that includes the necessary sources to supply the i.MX50. Its main 

features are: 

• Battery charger system for wall charging and USB charging 

• 10-bit ADC for monitoring battery and other inputs, plus a coulomb counter support module 

• Four adjustable output buck regulators for direct supply of the processor core and memory 

• 12 adjustable output LDOs with internal and external pass devices 

• Boost regulator for supplying RGB LEDs 

• Serial backlight drivers for displays and keypad, plus RGB LED drivers 




• Power control logic with processor interface and event detection 

• Real time clock and crystal oscillator circuitry, with coin cell backup and support for external secure real time 

clock on a companion system processor IC 

• Touch screen interface 

• SPI/I2C bus interface for control and register access 


Freescale Semiconductor 5


4.1 MC13892 Voltage supplies 

Supply Typical Application 

Table 2. MC13892 Voltage Supplies Summary 

4.2 MC13892 Power-up Sequence 

Output Voltage 

(in V) 

Load Capability 

(in mA) 

SW1 Buck regulators for processor core(s) 0.600-1.375 1050 

SW2 Buck regulators for processor SOG, etc. 0.600-1.375; 1.100-1.850 800 

SW3 Buck regulators for internal processor memory and 

peripherals 

SW4 Buck regulators for external memory and 

peripherals 

0.600-1.375; 1.100-1.850 800 

0.600-1.375; 1.100-1.850 800 

SWBST Boost regulator for USB OTG, Tri-color LED drivers 5.0 300 

VIOHI IO and Peripheral supply, eFuse support 2.775 100 

VPLL Quiet Analog supply (PLL, GPS) 1.2/1.25/1.5/1.8 50 

VDIG Low voltage digital (DPLL, GPS) 1.05/1.25/1.65/1.8 50 

VSD SD Card, external PNP 1.8/2.0/2.6/2.7/2.8/2.9/3.0/ 

3.15 

VUSB2 External USB PHY supply 2.4/2.6/2.7/2.775 50 

VVIDEO TV DAC supply, external PNP 2.5/2.6/2.7/2.775 350 

VAUDIO Audio supply 2.3/2.5/2.775/3.0 150 

VCAM Camera supply, internal PMOS 2.5/2.6/2.75/3.0 65 

Camera supply, external PNP 2.5/2.6/2.75/3.0 250 

VGEN1 General peripherals supply #1, external PNP 1.2/1.5/2.775/3.15 200 

VGEN2 General peripherals supply #2, external PNP 1.2/1.5/1.6/1.8/2.7/2.8/3.0/ 

3.15 

VGEN3 General peripherals supply #3, internal PMOS 1.8/2.9 50 

General peripherals supply #3, external PNP 1.8/2.9 250 

VUSB USB Transceiver supply 3.3 100 

The Power Up mode Select pins (PUMS1 and 2) are used to configure the startup characteristics of the regulators. 

Supply enabling and output level options are selected by hardwiring the PUMSx pins for the desired configuration. 

Tying the PUMSx pins to ground corresponds to 00, open to 01, VCOREDIG to 10, and VCORE to 11. 

The recommended power up strategy for end products is to bring up as little of the system as possible at booting, 

essentially sequestering just the bare essentials, to allow processor startup and software to run. With such a 

strategy, the startup transients are controlled at lower levels, and the rest of the system power tree can be brought 

up by software. This allows optimization of supply ordering where specific sequences may be required, as well as 

supply default values. Software code can load up all of the required programmable options to avoid sneak paths, 

under/over-voltage issues, startup surges, etc., without any change in hardware. For this reason, the Power Gate 

drivers are limited to activation by software rather than the sequencer, allowing the core(s) to startup before any 

peripheral loading is introduced. 


6 Freescale Semiconductor 

250 

350


The power up defaults Table 3 shows the initial setup for the voltage level of the switching and LDO regulators, 

and whether they get enabled. 

Table 3. Power Up Defaults Table 

PUMS1 GND Open VCOREDIG VCORE GND Open 

PUMS2 Open Open Open Open GND GND 

SW1 (1) 

SW2 (1) 

SW3 (1) 

SW4 (1) 

0.775 1.050 1.050 0.775 1.200 1.200 

1.025 1.225 1.225 1.025 1.350 1.450 

1.200 1.200 1.200 1.200 1.800 1.800 

1.800 1.800 1.800 1.800 1.800 1.800 

SWBST Off Off Off Off 5.000 5.000 

VUSB 3.300 (2) 

3.300 (2) 

3.300 (2) 

3.300 (2) 

3.300 (4) 

3.300 (4) 

VUSB2 2.600 2.600 2.600 2.600 2.600 2.600 

VPLL 1.800 1.800 1.800 1.800 1.500 1.500 

VDIG 1.250 1.250 1.250 1.250 1.250 1.250 

VIOHI 2.775 2.775 2.775 2.775 2.775 2.775 

VGEN2 3.150 Off 3.150 Off 3.150 3.150 

VSD Off Off Off Off 3.150 3.150 

Not initialized during power-up 

VCAM Off Off Off Off Off Off 

VGEN1 Off Off Off Off Off Off 

VGEN3 Off Off Off Off Off Off 

VVIDEO Off Off Off Off Off Off 

VAUDIO Off Off Off Off Off Off 

Notes 

1. The SWx regulators are activated in PWM pulse skipping mode, but allowed when enabled by the startup sequencer. 

2. USB supply VUSB, is only enabled if 5.0 V is present on UVBUS. 

3. The following supplies are not included in the matrix since they are not intended for activation by the startup sequencer: VCAM, VGEN1, 

VGEN3, VVIDEO, and VAUDIO 

4. SWBST = 5.0 V powers up and does VUSB regardless of 5.0 V present on UVBUS. By default VUSB will be supplied by SWBST. 




The power up sequence is shown in Table 4. VCOREDIG, VSRTC, and VCORE are brought up in the pre-sequencer 

startup. Once VCOREDIG is activated (i.e., at the first-time power application), it will be continuously powered as 

long as a valid coin cell is present. 

Table 4. Power Up Sequence 

Tap x 2ms PUMS2 = Open PUMS2 = GND 

0 SW2 SW2 

1 SW4 VGEN2 

2 VIOHI SW4 

3 VGEN2 VIOHI, VSD 

4 SW1 SWBST, VUSB (7) 

5 SW3 SW1 

6 VPLL VPLL 

7 VDIG SW3 

8 - VDIG 

9 VUSB (6) , VUSB2 VUSB2 

Notes 

5. The following supplies are not included in the matrix since they are not intended for activation by the startup 

sequencer: VCAM, VGEN1, VGEN3, VVIDEO, and VAUDIO. SWBST is not included on the PUMS2 = Open column. 

6. USB supply VUSB, is only enabled if 5.0 V is present on UVBUS. 

7. SWBST = 5.0 V powers up and so does VUSB regardless of 5.0 V present on UVBUS. By default VUSB will be 

supplied by SWBST. 



SW2 

SW4 

VIOHI 

VGEN2 

SW1 

SW3 

VPLL 

VDIG 

VUSB 

VUSB2 

Power on event 

2ms 2ms 2ms 2ms 2ms 2ms 2ms 4ms 


Figure 2. MC13892 Power up Sequence for i.MX50 processors. 




4.3 Interfacing the i.MX50 with the MC13892. 

Table 5, shows all the i.MX50 voltage rails, their power requirements and their associated MC13892 regulator. Most 

of the supply domains have flexible voltage and could be adjusted or supplied with a different regulator depending 

on each application needs 

Table 5. i,MX50 voltage domain supplies with the MC13892 

I.MX50 MC13892 

Power Rail of i.MX50 Power Domain TYP 

NVCCSRTC 32 kHz osc. power (when 

chip off) 

Associated 

Regulator 

Voltage 

PUM[4:0]=1110 

Current 

(mA) 

1.2 VSRTC 1.2 0.05 - 

VCC LP Transistor power 1.2 SW2 1.2 800 0 

VDDA Peripheral Memory + L2 

Cache power 

1.2 SW3 1.2 800 5 

VDDAL1 L1 Cache power 1.2 SW3 1.2 800 5 

VDDGP Core and G Transistor 

power 

1 SW1 1 1050 4 

VDDO2P5 Predriver for EMI pads 2.5 External LDO 2.5 250 - 

VDD2P5 Power to 24 MHz osc, 

efuse, xtalok, 

32 kHz osc. power mux 

2.5 External LDO 2.5 250 - 

NVCC_EMI_DRAM Power to EMI pins 1.2 External Buck 1.2 - - 

VREF DRAM Reference 0.9 Voltage divider 0.5 

x 

NVCC_EMI_DRA 

M 

NVCC EIM 

NVCC JTAG 

NVCC SPI 

NVCC SD 

NVCC NANDF 

NVCC SSI 

NVCC MISC 

NVCC KEYPAD 

ALL 3.3V IO NVCC 

NVCC EPDC 

NVCC LCD 

NVCC UART 

NVCC_SD2 

3.0 V I/Os 3 

3 

3 

3 

3 

3.0 V I/Os 

VDD3P0 VDD2P5 LDO input + 

power to Bandgap, 

DCDC predriver, 

tempsensor, 480 MHz PLL 

3.15 

3.15 

3.15 

3.15 



PUS 

1.2 * 0.5 250 - 

VGEN2 3.0 350 3 

External Buck 

VSD 

3.15 

3.15 

5000 

250 

3 VGEN2 3.0 350 3 

- 

-


USB_OTG_VDDA33 Power to USB Host 3.3 VUSB 3.3 100 9 

USB_H1_VDDA33 Power to USB OTG 3.3 VUSB 3.3 100 9 

All 1.8 IO NVCC 

VDD DCDCI 

VDD DCDCO 

1.8 V I/Os 

NVCC_RESET (LVIO) Power to 

POR_B,RESET_IN_B, 

TESTMODE, & 

BOOTMODE[0:1] 

1.8 

Not used 

1.875 or 

2.775 

SW4 1.8 800 1 

VPLL 1.8 50 6 

USB_OTG_VDDA25 Power to USB Host 2.5 VUSB2 2.5 50 9 

USB_H1VDDA25 Power to USB OTG 2.5 VUSB2 2.5 50 9 

VDD1P8 Power to all PLLs 1.8 VPLL 1.8 50 6 

VDD1P2 Power to all PLL digital, 32 

kHz osc. 

(when chip on), much of 

analog, digital 

Table 5. i,MX50 voltage domain supplies with the MC13892 

I.MX50 MC13892 

Power Rail of i.MX50 Power Domain TYP 

Associated 

Regulator 

Voltage 

PUM[4:0]=1110 

Current 

(mA) 

1.2 VDIG 1.2 50 7 



PUS


4.3.1 Interfacing Block Diagram 

The following block diagrams show all the power connections needed for the interface, as well as how the 

communication signals must be connected between the i.MX50 and MC13892. 

5.0V 

4.2V 

regulator 

VIN 

3.15V 

Buck 

regulator 

MC13892 

SW1 

SW2 

SW4B 

VUSB 

VUSB2 

VDIG 

VPLL 

VSW3 

VGEN2 

2.5V 

LDO 

2.5V 

LDO 

3.15V 

VDDGP 

VCC 

USB_VDDA33 

VDD2P5 

VDDO25 

Figure 3. i.MX50 Power Interface with MC13892 Block Diagram 



1.2V 

Buck 

i.MX50 

NVCC_EIM_DRAM 

USB_VDDA25 

VDD1P2 

VDD1P8 

NVCC_RESET 

VDDA 

VDDAL1 

VDD3P0 

NVCC_MISC 

NVCC_SPI 

NVCC_SD1 

NVCC_NANDF 

NVCC_KEYPAD 

NVCC_SSI 

NVCC_JTAG 

NVCC_UART 

NVCC_LCD 

NVCC_EPDC 

Peripherals 

CODEC 

HDMI 

ETHERNET 

3G PCIe 

RS-232

MC13892 

RESETBMCU 

RESETB 

STANDBY 

POWERON1 

WDI 

INT 

UID 

CKL 

MISO/SDA 

4.3.1.1 3.15 V Buck Regulator 


Figure 4. i.MX50 Control Interface with MC34709 Block Diagram 

For system stability, it is recommended that you use an extra 3.15 V DCDC power supply to support large current 

requirements (for example a 3G module or Wi-Fi card). The MC34709 has limited 3.15 V output ability. 

4.3.1.2 1.2 V Buck Regulator 

SWx 

POR_B 

WDOG 

CLK32MCU CLK 

PUMS1 

PUMS2 

SWx 

SWx 

VCOREDIG 

GPIOX_X 

i.MX50 

RESET_IN_B 

PMIC_STBY_REQ 

PMIC_ON_REQ 

USB_OTG_ID 

CSPI_SCLK 

CSPI_MISO/MOSI 

A 1.2V Buck regulator is required to provide voltage to the 1.2V LPDDR2 module and the NVCC_EMI_DRAM 

domain in the i.MX50 processor. Regulator SW4 will supply the input of this regulator at 1.8V and will also be used 

as the 1.8V supply on the LPDDR2 Module as well. 



NC


4.3.1.3 2.5 V LDO Regulators 

Due to the Power-up sequence dependency, two 2.5V LDO regulators are required to power up the VDD2P5 and 

VDDO25 domains in the i.MX processor. The first one is enabled by the SW2 voltage rail, while the second LDO is 

enabled with the VGEN2 voltage rail. See Figure 3. 

4.3.2 Interface Power-up Sequence 

The resulting power-up sequence of the interface is shown in the following figure 

VDD2P5 

NVCC_EMI 

_DRAM 

VDDO25 

3.3V NVCC 

I/O 

NVCC_EPDC 

NVCC_LCD 

NVCC UART 


USB_H1_VDDA33 

NVCCSRTC VSRTC 

VCC SW2 

1.8 NVCC I/O rails 

VDD DCDCI 

VDD DCDCO 

N/A 

VDD3P0 

NVCC EIM 

NVCC JTAG 

NVCC SPI 

NVCC SD 

NVCC NANDF 

NVCC SSI 

NVCC MISC 

NVCC KEYPAD 

VDDGP 

VDDA 

VDDAL1 

VDD1P8 

NVCC_RESET (LVIO) 

VDD1P2 


USB_H1VDDA25 

SD2 

2.5V 

LDO 

regulator 

1.2V 

DC-DC 

regulator 

2.5V 

LDO 

regulator 

Figure 5. Power up Sequence Flow Chart 



3.15V 

Buck 

regulator 

VUSB 

SW4 

VIOHI 

VGEN2 

SW1 

SW3 

VPLL 

VDIG 

VSD* Enabled via 

SPI 

VUSB2

4.4 Application Example with the MC13892 


The following schematic is simplified application example for interfacing the MC13892 with an i.MX50 processor. 

note that this schematic only includes the block related to the power section as well as power management 

controlling signals. 

U12E 

JP3 

HDR 1X2 

DNP 

PCIMX508DJV1A 

VDDGP 

3V_VGEN2 

SH4 

DNP 

VDD2P5 

1V8_ANA_PLL 

GND 

GND 

VDD3P0 

VDD2P5 

VDD1P8 

i.MX50 - POWER 

VDDGP_1 

C68 

C70 C86 

0.22UF 

0.22UF 0.22UF 

GND 

VCC 

1V2_SW2 

1V2_DIG GND 

VDD1P2 

C81 C82 

22UF 0.1UF 

C76 

C91 C78 

C80 

0.22UF 

0.22UF 0.22UF 

10UF 

GND 

1V2_SW3 

SH5 

0 

1V8_SW4 

GND 

VDDA 

C94 

SH9 

0 

SH6 

DNP 

C84 

VDD_DCDCI 

0.1UF 

0.1UF 

GND 

GND 

VDDA_L 

SH10 

0 

DNP 

TP11 2.2UH 2 L8 1 VDD_DCDCO 

GND 

GND 

SH11 

0 

VDDO2P5 

GND 

G8 

VDDGP_2 G9 

VDDGP_3 G10 

VDDGP_4 H8 

VDDGP_5 H9 

VCC_1 H14 

VCC_2 H15 

VCC_3 H16 

VCC_4 H17 

J17 

VCC_5 K14 

VCC_6 K15 

VCC_7 

P17 

VDDA_1 

VDDA_2 R17 

VDDGP_6 H10 

VDDGP_7 

K17 

VCC_8 

W5 

GND_DCDC 

H11 

J8 

VDDGP_8 K7 

VDDGP_9 K8 

VDDGP_10 

K10 

VDDGP_11 K11 

VDDGP_12 L8 

VDDGP_13 L10 

VDDGP_14 L11 

VDDGP_15 

L15 

VCC_9 

P15 

VDDAL_1 

VDDAL_2 R15 

Y6 

VDD_DCDCI 

Y5 

VDD_DCDCO 

VDDO25 N23 

SH8 

DNP 

C89 

C66 

0.1UF 

C74 

0.1UF 

C75 

AD3 

VDD3P0 

AD4 

VDD2P5 

AD7 

VDD1P8 

C67 

C69 C85 

C87 C71 C88 C72 C73 SH7 

0 

0.22UF 

0.22UF 0.22UF 

0.22UF 0.01UF 0.01UF 10UF 22UF 

JP2 

HDR 1X2 

DNP 

0.1UF 22UF 

AD6 

VDD1P2 

C90 C77 

C92 C79 

0.22UF 0.22UF 

0.01UF 0.01UF 

C93 

22UF 

C83 

0.1UF 

C95 C96 

0.1UF 0.1UF 

C98 

C97 DNP 

68uFDNP 0.1UF 

C99 

0.1UF 

3V_VGEN2 

SH12 

DNP 

3V_VGEN2 

SH14 

DNP 

DCDC_3V15 

SH15 

DNP 

3V_VGEN2 

SH17 

DNP 

DCDC_3V15 

SH19 

DNP 

3V_VGEN2 

SH21 

DNP 

3V15_VSD 

SH23 

DNP 

3V_VGEN2 

SH25 

DNP 

3V_VGEN2 

SH27 

DNP 

GND 

NVCC_KEYPAD 

C100 

0.1UF 

GND 

NVCC_LCD U11 

NVCC_LCD 

C128 

0.1UF 

GND 

NVCC_NANDF 

C131 C132 

0.1UF 0.1UF 

NVCC_SD2 U8 

NVCC_SD2 

C135 

0.1UF 

GND 

NVCC_SD1 T7 

NVCC_SD1 

C137 

0.1UF 

GND 

NVCC_SPI R7 

NVCC_SPI 

C145 

0.1UF 

GND 

N8 

NVCC_KEYPAD 

GND 

NVCC_MISC P8 

NVCC_MISC 

C113 

0.1UF 

GND 

NVCC_UART T8 

NVCC_UART 

C117 

0.1UF 

GND 

NVCC_SSI R8 

NVCC_SSI 

C127 

0.1UF 

V10 

V9 

NVCC_NANDF2 

NVCC_NANDF1 

AA2 

NGND_SRTC 

AC6 

GND1P2 

GND_KEL 

AA7 

AC3 

AC7 GND3P0 

AC4 GND1P8 

GND2P5 

GND 

A21 

NVCC_EMI_DRAM_1 

B21 


NVCC_EMI_DRAM_3 D21 



K21 


K23 

NVCC_EMI_DRAM7 


L7 

NVCC_EIM1 

R21 

NVCC_EMI_DRAM10 R23 


K24 


AA21 

NVCC_EMI_DRAM12 AA23 

NVCC_EMI_DRAM13 AA24 

NVCC_EMI_DRAM14 AC21 

NVCC_EMI_DRAM15 AD21 


NVCC_EIM2 M7 

NVCC_EIM3 M8 

VSS1 

VSS2 

VSS3 

VSS4 

VSS5 

VSS6 

VSS7 

VSS8 

VSS9 

VSS10 

VSS11 

VSS12 

VSS13 

VSS14 

VSS15 

VSS16 

VSS17 

VSS18 

VSS19 

VSS20 

VSS21 

VSS22 

VSS23 

VSS24 

VSS25 

VSS26 

VSS27 

VSS28 

VSS29 

VSS30 

VSS31 

VSS32 

VSS33 

VSS34 

VSS35 

VSS36 

VSS37 

VSS38 

VSS39 

VSS40 

VSS41 

VSS42 

VSS43 

VSS44 

VSS45 

VSS46 

VSS47 

VSS48 

VSS49 

VSS50 

VSS51 

VSS52 

VSS53 

VSS54 

A1 

A18 

A24 

B18 

G20 

G21 

G23 

H12 

H13 

K12 

K13 

L12 

L13 

L14 

L17 

M11 

M14 

M15 

M17 

M18 

M20 

M21 

N11 

N14 

N15 

N17 

P11 

P12 

P13 

P14 

R11 

R12 

R13 

R14 

T17 

T18 

U12 

U13 

U14 

U15 

U16 

U17 

U18 

V17 

V18 

V20 

V21 

V23 

AA9 

AA11 

AC18 

AD1 

AD18 

AD24 

NVCC_EPDC1 M10 

NVCC_EPDC2 N10 

P10 

NVCC_EPDC3 

NVCC_EPDC4 R10 

NVCC_EPDC5 U10 

AC9 

USB_OTG_VDDA25_1 AD9 

USB_H1_VDDA25_1 

GND 

3V_VGEN2 

NVCC_JTAG 

NVCC_JTAG 

R56 

DNP 

0 

1V8_SW4 

GND 

1V8_ANA_PLL 

NVCC_RESET 

C146 

0.1UF 

U9 

C138 

0.1UF SH26 

DNP 

V8 

NVCC_RESET 

SH28 

DNP 

Figure 6. i.MX50 Voltage Domains 



GND 

GND 

AD11 

USB_OTG_VDDA33 AC11 

USB_H1_VDDA33 

C129 

0.1UF 

C133 

0.1UF 

GND 

GND 

SH22 

DNP 

C134 

0.1UF 

GND 

NVCC_SRTC 

SH24 

NVCC_SRTC 

DNP 

C136 

0.1UF 

AA1 

C101 C102 C103 C104 C105 C106 C107 C108 C109 C110 C111 C112 

0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.01UF 0.01UF 10UF 10UF 

NVCC_EIM 

C114 C115 C116 C118 C119 C120 

SH16 

DNP 

0.1UF 0.1UF 0.1UF 0.01UF 0.01UF 10UF 

GND 

NVCC_EPDC 

C121 C122 C123 C124 C125 C126 

SH18 

DNP 

0.1UF 0.1UF 0.1UF 0.1UF 0.01UF 10UF 

SH20 

DNP 

C130 

0.1UF 

GND 

3V3_USB 

2V5_VUSB2 

1V2_RTC 

1 

2 

3V_VGEN2 

DCDC_3V15 

1 

2 

1V_SW1 

JP4 

HDR 1X2 

DNP 

1V2_DDR 

1 

2 

SH13 

0 

3V_VGEN2 

C143 C144 

22UF 0.01UF 

GND 

ICAP Classification: 

Drawing Title: 

FCP: ___ FIUO: X 

i MX50 Reference Des


PCB MOD: 

Cut Trace 

4,5 

Touch Screen 

Connector 

VCC_BP 

Sensitive analog lines. 

X1-X2 and Y1-Y2 

make differential pairs. 

Note: use 10uF for Coulomb Counting of a battery. 

DNP if not required. 

4,8 CSPI_SS0 

1,15 CSPI_SCLK 

1,15 CSPI_MOSI 

1,15 CSPI_MISO 

BATT_NTC 

4,9 PMIC_STBY_REQ 

SH83 

0 

DNP 

3V3_USB 

(PUS_9) 

SWBST 

5V_APL 

R3 DNP 10K 

5V_APL 

3 2 

1 

GND 

GND 

R19 0 

- 

+ 

B1 

B2 

A2 

C1 

C2 

BT1 

2994TR 

R7 

47K 

DNP 

R17 0 

DNP 

1V2_RTC 1V8_SW4 

LI-ION_BATTERY 

GPO1 

BATTISNS 

U6 

NLSV1T34 

GND 

Q3 

FDZ193P 

A1 

GND GND 

TP5 

GND 

C39 0.1UF 

GND 

Coin cell. 

C42 

C43 

0.1UF 

0.1UF 

GND 

GND 

BATTFET 

(active high) 

R26 0 

BATTISNS 

B12 

BATTISNSCC 

K7 

C22 

CFP 

10UFK8 

CFM 

VCC_BP 

R1 0.02 

C1 C2 

10UF 2.2uF 

GND 

3V_VGEN2 

K2 

L2 SPIVCC 

R14 100K 

DNP 

M2 

J2 

H2 

H4 

CS 

CLK 

MOSI 

MISO 

GNDSPI 

SPI/I2C 

interface 

R15 

2.775V C25 2.2UF VCORE 

GND 

A9 

VCORE 

4.7K 1.5V C27 2.2UF VCOREDIG B9 

VCOREDIG Reference 

1.2V C28 0.1UF REFCORE D7 

B8 

Generation 

REFCORE 

GNDCORE 

GND 

GND 

GND 

1 

VCCA 

2 

A 

R18 DNP 0 

R21 0 

3 

GND 

6 

VCCB 

4 

B 

NC 5 

TP4 

C37 2.2UF 

R4 0.02 

GND 

VCOREDIG R23 DNP 0 

R24 0 

GND VCORE R28 DNP 0 

VCOREDIG R29 0 

R30 DNP 0 

GND 

CHRGISNS 

CHRGCTRL 

CHRGCTRL1 

TO-2.0A 

R20 10M 

Y1 

TP59 

GND 2 

1GND 

TP8 

R22 

GND 

C44 

C45 

32.768KHz 

0 

GPO1 1V2_RTC 

15pF 

15pF 

2 

D1 

B1 

B2 

A2 

LED_ORANGE 

PWRON2 

1 

A1 C1 

C2 

R27 4.7K 

R25 0 

Figure 7. MC13892 Schematic 

5V Selection 

ECKIL 4,9 

C46 

RESET_IN_B 4,9,15 

POR_B 4,9 

3V_VGEN2 

1uF 1V2_RTC 

U5 

GND 

5 

VCC 

1 

PMIC_ON_REQ 4,9 

WDOG_B 4,8 

PWR_INT(GP4_18) 4,8 

2 

PWRON3 

PWRON1 

4,15 

4 

4,9 Open-drain required 

3 

GND 

NC7SP125P5X 

GND 

1.2V LPDDR2 



Q1 

FDZ193P 

5V_APL 

GND 

C6 

0.1UF 

C2 

A1 C1 

A2 

B2 

B1 

R6 0 

DNP 

C7 

10UF 

C8 C9 

10UF 10UF 

GND 

U2 GND GND MC13892 

R8 10K R9 

10K 

Battery 

Interface & 

Protection 

J6 

GND 

GNDADC 

R320 

DNP 

4,5 

0 

TP3 

BATT_NTC 

K9 

GND K10 

M11 

ADIN5 

ADIN6 

ADIN7 

4,15 TOUCH_X0 

4,15 TOUCH_X1 

4,15 TOUCH_Y0 

4,15 TOUCH_Y1 

C20 

J9 

J12 

M12 

L12 

M13 

N12 

N13 

TSX1 

TSX2 

TSY1 

TSY2 

TSREF_1 

TSREF_2 

TSREF_3 

Touch 

Screen 

interface 

2.2UF 

E11 

ADTRIG 

A10 

BATT 

E6 

E1 

UID 

UVBUS 

F2 

VBUSEN 

G2 

VINUSB 

D1 

VUSB 

D9 

LICELL 

BATTISNS C13 

VUSB 

100mA 

GNDSUB1 

GNDSUB2 

GNDSUB3 

GNDSUB4 

GNDSUB5 

GNDSUB6 

GNDSUB7 

GNDSUB8 

GNDSUB9 

F6 

F7 

F8 

G6 

G7 

G8 

H6 

H7 

H8 

BATTFET D10 

B10 

BP 

BPSNS D12 

CHRGISNS C12 

A12 

CHRGCTRL2_1 

B11 

CHRGCTRL1 

CHRGRAW A11 

A13 

CHRGCTRL2_2 B13 

CHRGCTRL2_3 

N6 

XTAL1 

Charger 

Interface 

and Control 

CHRGLED E9 

CHRGSE1B D8 

GNDCHRG E8 

XTAL2 

GNDRTC 

GNDCTRL 

MODE 

PUMS1 

PWRON1 

PWRON2 

PWRON3 

STANDBY 

INT 

WDI 

RESETBMCU 

RESETB 

STANDBYSEC 

N5 

M5 

H9 

A8 

G9 

D13 

E10 

J8 

J5 

E12 

G10 

F11 

F12 

H12 

NC A7 

LEDMD D5 

LEDAD F5 

B6 

LEDKP 

GNDSWLED A6 

Backlight 

LED Drive 

CLK32K 

CLK32KMCU 

VSRTC 

K5 

J4 

M4 

LEDR B7 

LEDG E4 

B5 

LEDB 

GNDLED E5 

D6 

DVS1 

DVS2 

B3 

J7 

GNDREG1 

GNDREG2 

VGEN3_2 

B2 

F10 GPO1 

F9 GPO2 

G12 

GPO3 

GPO4 

H5 

G5 

GNDREG3 

DNP 

Q2 

FDZ193P 

SH30 

5V_APL 

APL_GPIO2 5 

CHGR_DET_B_TO_PMIC 8 

C10 

4.7uF 

C19 10UF 

3 2 

VCC_BP 

C11 

4.7uF 

5V_APL 

C12 

4.7uF 

4 

SH88 0 

1 

2 

5 

6 

R313 0 

DNP 

C13 

4.7uF 

4 

1 

2 

5 

6 

4 

5V_MAIN 

USB_5V 

1 

2 

5 

6 

4 

1 

2 

5 

6 

1V8_SW4 

GND GND GND 

GND 

Put 4.7UF capacitors at pins G13, H13, H1 and J1. 

K4 

PWGTDRV1 

Tri-Color 

LED Drive 

PWGTDRV2 

VCC_BP 

(PUS_4) 

+/- 1% 

1V_SW1 

SW1 

1050mA 

Buck 

VCC_BP 

1.5UH 

1L2 R10 

2 

0 

C17 10UF 

SW1 

GND 

(PUS_0) 

1V2_SW2 

SW2 

800mA 

Buck 

1L3 R11 

VCC_BP 

2.2UH 2 

0 

C18 10UF 

GND 

SW2 

(PUS_5) 

1V2_SW3 

SW3 

800mA 

Buck 

1L4 VCC_BP 

2.2UH 2 

GND 

SW3 

(PUS_1) 

1V8_SW4 

SW4 

800mA 

Buck 

1L5 2.2UH 2 

C21 10UF 

GND 

SW4 

VCC_BP L6 3.3uH 

VCC_BP SWBST 

1 

D2 

2.2uH 2 is for optional 

VCC_BP 

SWBST 

350mA 

2 1 

MBR120LSFT1G 

C23 10uF 

GND 

3 NSS12100XV6T1G 

2V775_VVIDEO 

Boost 

VVIDEO 

350mA 

VUSB2 

50mA 

VAUDIO 

150mA 

VVIOHI 

100mA 

VVIDEODRV 

VCC_BP C24 2.2UF 

GND 

C26 2.2UF 

VCC_BP 

GND 

3V_VAUDIO 

UNUSED 

VCC_BP C31 2.2UF 

2V775_VIOIH 

(PUS_2) UNUSED 

C32 2.2UF GND 

VCC_BP 

Q6 

(PUS_9) 2V5_VUSB2 

NOTE: (PUS_X) means the Power Up 

Sequence index number during turn on. 

VPLL 

50mA 

VDIG 

50mA 

VCAM 

250mA 

VCC_BP C33 

C34 

VCAMDRV 

C35 

1V8_ANA_PLL 

GND(PUS_6) 

VCC_BP 

2.2UF 

Q7 

1V2_DIG 

NSS12100XV6T1G 

(PUS_7) 

DNP 

2.2UF GND 

3 UNUSED 

VCC_BP 

3V_VCAM 

GND 

Q8 

2.2UF 


GND 

3 

VCC_BP 

VSD 

250mA 

VGEN1 

200mA 

VSDDRV 

C36 

VGEN1DRV 

C38 

2.2UF 

2.2UF 

GND 

GND 

3V15_VSD 

3 

Q9 


DNP VCC_BP 

UNUSED 

3V_VGEN1 Q10 

NSS12100XV6 

3 

VGEN2 

350mA 

VGEN3 

50mA 

VGEN2DRV 

C40 

VGEN3DRV 

2.2UF 

GND 

VCC_BP 

Q11 

NSS12100UW3 

(PUS_3) 

3V_VG 

C41 

DNP 

2.2UF 1 UNUSED 

1V8_VGEN3 

GND 

M7 

SW1IN G13 

F13 

SW1OUT 

SW1FB E13 

GNDSW1 

H10 

SW2IN H13 

J13 

SW2OUT J10 

SW2FB K13 

GNDSW2 

SW3IN H1 

SW3OUT G1 

F4 

SW3FB F1 

GNDSW3 

SW4IN J1 

K1 

SW4OUT 

SW4FB L1 

GNDSW4 

G4 

SWBSTIN A4 

B4 

SWBSTOUT 

SWBSTFB D4 

A5 

GNDSWBST 

VVIDEODRV 

VVIDEO 

K12 

L13 

VINUSB2 

VUSB2_1 

VAUDIO 

A3 

A1 

N8 

VINIOHI N10 

VIOHI N9 

VPLL 

VINDIG 

E2 

M9 

VDIG M8 

VCAMDRV M6 

VCAM K6 

VSDDRV C2 

VSD D2 

VGEN1DRV M10 

VGEN1 N11 

VGEN2DRV N4 

VGEN2 M3 

VINGEN3DRV N3 

VGEN3_1 M1 

VUSB2_2 

VUSB2_3 

A2 

B1 

VINPLL C1 

PUMS2 

E7 

VGEN3_3 

N1 

N2 

VINAUDIO N7 

4 

SH85 

0 

1 

2 

5 

6 

GND

VSOURCE 

SH1 

0 

C47 + C48 + C49 + C50 

100UF 100UF 100UF 4.7uF 

Note: Freq=1Mhz, Tsoftstart=3.2ms 

3V_VGEN2 

R33 

10.0K 

SH71 

DNP 

C51 

0.1UF 

VDDI 

GND 

U7 

18 

19 

20 

GND 

5 

VIN1 

NC1 

VIN2 

BOOT 

21 

DDR2/DDR3 Power 

0.7V 

GND 

VDDI 

24 

VDDI 

PG 

MC34713EP 

4 

8 

NC2 

7 

VREFIN 

VOUT 

11 

3 

ILIM 

2 

FREQ 

COMP 

6 

SD 

9 

INV 10 

R31 

9.31K 

PVIN1 PVIN2 PVIN3 

C53 0.1UF 

C54 

0.1UF 

R34 5.1K 

SW1 

SW2 

SW3 

15 

16 

17 

1 L7 

1.0UH 

2 

R37 0 

C55 

R38 15K 

R41 10K 

R42 DNP4.99K 

20PF C56 560PF 

PGND1 PGND2 PGND3GND1 

GND2 

C61 

12 13 14 1 25 

0.1UF 

1V8_SW4 

22 

23 

Figure 8. 3.15V Buck Regulator 

SH85 

0 

GND 

SH86 

C3 

10uF 

SH84 DNP 

3 

U1 

LTC3409EDD 

VIN1 

MODE 

5 

DNP 7 

RUN 

4 

VIN2 

2 

GND 

9 

E_PAD 

Vout = 0.613 * [ R(Vout-Vfb) / R(Vfb-Gnd) + 1 ] 

Vout = 1.2V for R(Vout-Vfb) = 127K & R(Vfb-Gnd)=133K 

Figure 9. 1.2V Buck Regulator 

VDDO2P5 LDO 

VSOURCE 

C16 

2.2uF 

GND 

VDD2P5 LDO 

3V_VGEN2 

GND 

C15 

100 PF 

Figure 10. 2.5V LDO Regulators 


Vout = 0.7 * [ R(sw-inv) / R(inv-gnd) + 1 ] 

Vout = 3.14V for R39=17.4K, R44=4.99K 



GND 

SW 6 

1 

VFB 

SYNC 8 

Q4 

IRLML6401 

VSOURCE 

3 2 

R306 

100K 

GND 

1V2_SW2 

R13 10K 1 

10K 

R16 

C30 

100 PF 

1 

U3 

VIN 

5 

VOUT 

C14 

4 

BYP 

4.7uF 

3 

ON/OFF 

2 

GND 

LP2992 

GND 

1 

2 3 

Q5 

MMBT3904 

R307 

100K 

1 

U4 

VIN 

5 

VOUT 

C29 

4 

BYP 

22UF 

3 

ON/OFF 

2 

GND 

LP2992 

GND 

L1 2.2UH 

1 2 

SH87 

DNP 

R2 

127.0K 

R5 

133.0K 

VDDO2P5 

VDD2P5 

1V2_DDR 

C4 

20PF C5 

10uF 

R35 

4.12K 

C57 

470pF 

R39 

17.4K 

R44 

4.99K 

C58 + 

100UF 

SH2 

0 

C59 + C60 + 

100UF 100UF 

DCDC_3V15


BOOT_MODE0 

BOOT_MODE1 

R73 

10K 

GND 

4,6 PMIC_STBY_REQ 

4,6 PMIC_ON_REQ 

C148 

18PF 

DNP 

4,6 

4,6 POR_B 

RESET_IN_B 

4,6,15 

QZ1 

1 2 

32.768KHZ 

DNP 

GND 

ECKIL 

C149 

18PF 

DNP 

AD2 

POR_B 

AB1 

AB2 BOOT_MODE0 

BOOT_MODE1 

RESET_IN_B 

AC1 

AC2 

TEST_MODE 

Y2 

ECKIL 

CKIL 

W2 

W1 

PMIC_STBY_REQ 

PMIC_ON_REQ 

Y1 

SH31 

SH0603 

DNP 

U12C 

PCIMX508DJV1A 

i.MX50 - CONTROL PINS 

Figure 11. i.MX50 Control Signals 

4.5 MC13892 PCB Layout Example 

NVCC_RESET 

NVCC_RTC 

NVCC_JTAG 

JTAG_TCK JTAG_TCK 

JTAG_TMS 

JTAG_TDI 

JTAG_TDO 

JTAG_TRST_B 

W4 

JTAG_TMS 

JTAG_TDI 

JTAG_TDO 

Y4 

AA4 

U7 

JTAG_TRSTB 

JTAG_MOD 

AA5 

V7 

CKIH AA6 SH33 DNP 

The following example shows the PMIC layout section for a reference design of the i.MX50 using the MC13892 

power management. It is design in 10 layers with 4 inner planes (GND and PWR) form layer 4 to layer 7. For 

simplicity, only top, bottom and Inner signal layers are shown in figures x to y. 

1 

TP 

SH 

R31910 

4 

C48 

TP4 

TP5 

C47 L4 

L5 

C49 

C21JP3 

SH13 

R93 

R92 

C37 

R316 

JP4 

1 

R66 

1 

S 

R315 

L6 

1 

D2 

1 

1 

1C40 

R20 

C411 

R76 

C44 

C45 

R67 

R62 

S 

U2 

S 

AC5 

EXTAL 

XTAL 

AD5 

Y1 

Figure 12. Top Fabrication Drawing 



C7 

1 

GND 

Y2 

4 GND 3 

1 2 

GND 

C152 

15PF 

1 

C 

R74 1.0M 

24MHZ 

C38 

C31 

R1 

TP8 

C22TP3 

C154 

1 

Y3 

TP15 

GND 

JTAG_MOD 

1V8_SW4 

GND 

R85 

10K 

DNP 

R86 

1K 

OSC. 

Y3 

VCC 

10K 

C153 

15PF 22.5792MHZ 

DNP 

4 

3 

OUT 

DGND 2 

EN/DIS 

1 

AL2 

1 

1 

R76 

1V8_ANA_PLL 

C154 

0.1UF 

GND 

R16 

1U6 

U4 

TP59 

TP17 

TP20 

SH31 

R21 

L3 

C2 

1 

C233 

TP18 

101 

C1 

SH79 

J20 

TP23 

TP21 

5 

C30 

4 

1 

L9 

2 

JP5 

+ 

C 

1

C121 

C124 

C1 

SH1 

C130 

C129 

C133 

C134 

20 

4 

C10 

C1 

SH6 

C116 

C114 

JP4 

C119 

C118 

C89 

C138 

10 

C84 

C148 

JP3 

SH2 

C19 

R18 

R19 

R15 

C75 

SH20 

R63 

SH26 

SH7 

Q8 

Q11 

Q10 

SH8 

40 

R17 

1 

1 

C12 

Q7 

SH4 

R7 

C35 

C34 

R320 

Figure 13. Bottom Fabrication Drawing 

Figure 14. Top Layer 




C32 

Q6 

30 

C39 

R11 

R10 

Q9 

TP15 

C6 

C20 

20 

10 

R30 

SH83 

R27 

R25 

R26 

C43 

C42 

C29 

U5 

10 

2 

J20 

1 

2 

1 

C46 

BT1 

1 

1 

5 

2 

1 

R29 

R28 

C18 

C17 

1 

R22 

1 

5 

1 

15 

JP5 

17 

1 

1 

1 

1 

1 

2 

1 

1 

1 

1 

1 

1 

1 

1 

C 

A 

1 

1 

1 

1 

101 

5 

4 

1 

2 

+ 

1


Figure 15. Inner Layer 2 (Signal) 










40 

2 

20 

10 

1 

1 

1 

1 

1 

Figure 19. Bottom Layer 



30 

20 

10 

1 2 

1 

1 

1 

5 

2 

1 

1 

1 

15 

17 

1

i.MX50 Power Management Design with the MC34709 

5 i.MX50 Power Management Design with the MC34709 

The MC34709 is a power management IC that includes the necessary sources to supply the i.MX50. Its main 

features are: 

• Ten-bit ADC for monitoring. 

• Four-wire resistive touchscreen interface 

• Five buck converters for direct supply of the processor core and memory 

• One boost converter for USB OTG support 

• Eight LDO Regulators with internal and external pass devices for thermal budget optimization 

• Power control logic with processor interface and event detection 

• Real time clock and crystal oscillator circuitry with coin cell backup 

• Support for external secure real time clock on a companion system processor IC 

• Single SPI/I2C bus for control & register access 

• Four general purpose low voltage I/Os with interrupt capability 

• Two PWM outputs 

5.1 MC34709 Voltage supplies 

Supply Typical Application 

Table 6. MC34709 Voltage Supplies Summary 

Output Voltage 

(in V) 

Load Capability 

(in mA) 

SW1 Buck regulator for processor VDDGP domain 0.650 - 1.4375 2000 

SW2 Buck regulator for processor VCC domain 0.650 - 1.4375 1000 

SW3 Buck regulator for processor VDD domain and peripherals 0.650 - 1.425 500 

SW4A Buck regulator for DDR memory and peripherals 1.200 – 1.975: 2.5/3.15/3.3 500 

SW4B Buck regulator for DDR memory and peripherals 1.200 – 1.975: 2.5/3.15/3.3 500 

SW5 Buck regulator for I/O domain 1.200 – 1.975 1000 

SWBST Boost regulator for USB OTG 5.00/5.05/5.10/5.15 380 

VSRTC Secure Real Time Clock supply 1.2 0.05 

VPLL Quiet Analog supply 1.2/1.25/1.5/1.8 50 

VREFDDR DDR Ref supply 0.6-0.9V 10 

VDAC TV DAC supply, external PNP 2.5/2.6/2.7/2.775 250 

VUSB2 VUSB/peripherals supply, internal PMOS 2.5/2.6/2.75/3.0 65 

VUSB/peripherals external PNP 2.5/2.6/2.75/3.0 350 

VGEN1 General peripherals supply #1 1.2/1.25/1.3/1.35/ 

1.4/1.45/1.5/1.55 

VGEN2 General peripherals supply #2, internal PMOS 2.5/2.7/2.8/2.9/3.0/ 

3.1/3.15/3.3 

General peripherals supply #2, external PNP 2.5/2.7/2.8/2.9/3.0/ 

3.1/3.15/3.3 

VUSB USB Transceiver supply 3.3 100 



250 

50 

250


5.2 MC34709 Power-up Sequence 

The MC34709 has 5 PUMS signals that enable to program the power up sequence as well as the default output 

voltage for specific rails, making the part suitable to supply DDR2, DDR3, LPDDR2, LVDDR3 memories with the 

correct power up sequence for many processors of the i.MX family. The following table shows the power up 

sequence and all possible voltage combinations to supply the i.MX50 in all possible modes. 

Table 7. Power-up Defaults 

i.MX50 mDDR LPDDR2 LPDDR2 mDDR LPDDR2 mDDR 

PUMS[4:1] 1010 1011 1100 1101 1110 1111 

PUMS5=0 

VUSB2/VGEN2 

PUMS5=1 

VUSB2/VGEN2 

SW1A 

(VDDGP) 

SW1B 

(VDDGP) 

SW2 (8) 

(VCC) 

SW3 (8) 

(VDDA) 

SW4A (8) 

(DDR/SYS) 

SW4B (8) 

(DDR/SYS) 

SW5 (8) 

(I/O) 

VUSB (9) 

Ext PNP Ext PNP Ext PNP Ext PNP Ext PNP Ext PNP 

Internal 

PMOS 

Internal 

PMOS 

Internal 

PMOS 

Internal 

PMOS 

Internal 

PMOS 

Internal 

PMOS 

1.1 1.1 1.1 1.1 1.1 1.1 

1.1 1.1 1.1 1.1 1.1 1.1 

1.2 1.2 1.2 1.2 1.2 1.2 

1.2 1.2 1.2 1.2 1.2 1.2 

1.8 1.2 3.15 3.15 3.15 3.15 

1.8 1.2 1.2 1.8 1.2 1.8 

1.8 1.8 1.8 1.8 1.8 1.8 

3.3 3.3 3.3 3.3 3.3 3.3 

VUSB2 2.5 2.5 2.5 2.5 2.5 2.5 

VSRTC 1.2 1.2 1.2 1.2 1.2 1.2 

VPLL 1.8 1.8 1.8 1.8 1.8 1.8 

VREFDDR On On On On On On 

VDAC 2.5 2.5 2.5 2.5 2.5 2.5 

VGEN1 1.2 1.2 1.2 1.2 1.2 1.2 

VGEN2 3.1 3.1 3.1 3.1 2.5 2.5 

Not used on System 

SWBST Off Off Off Off Off Off 

Notes 

8. The SWx node are activated in APS mode when enabled by the start-up sequencer. 

9. VUSB is supplied by SWBST. 




VCOREDIG, VSRTC, and VCORE, are brought up in the pre-sequencer start-up. See Figure 2 

System Core Active 

Turn On Verification 

Power Up Sequencer 

UV Masking 

RESETB 

WDI 

Turn On Event 

INT 

1 - Off 

Tap x 

2.0 ms 

Table 8. Power-up Sequence i.MX50 

PUMS [4:1] = [0100, 1011, 1100, 1101, 1110, 1111] 

0 SW2 

1 SW3 

2 SW1A/B 

3 VDAC 

4 SW4A/B, VREFDDR 

5 SW5 

6 VGEN2, VUSB2 

7 VPLL 

8 VGEN1 

9 VUSB 

Sequencer time slots 

8 ms 8 ms 

20 ms 12 ms 

2 - Cold Start 

Figure 20. Complete MC34709 Power-up Sequence 



128 ms 

WDI Pulled Low 

3 - Watchdog 4 - On 3- Watchdog 1 - Off 

Power up of the system upon a Turn On Event followed by a transition to the On state if WDI is pulled high ... or transition to Off state if WDI remains low 

Turn on Event is based on PWRON being pulled low 

= Indeterminate State 

ow


SW2 

SW3 

SW1A/B 

VDAC 

SW4A/B 

VREFDDR 

SW5 

VGEN2 

VUSB2 

VPLL 

VGEN1 

VUSB 

Power on event 

2ms 2ms 2ms 2ms 2ms 2ms 2ms 

2ms 2ms 

Figure 21. MC3709 Power up Sequence for i.MX50 processors. 



5.3 Interfacing the i.MX50 with the MC34709 


Table 9, shows all the i.MX voltage rails, their power requirements and their associated MC34709 regulator. Most of 

the supply domains have flexible voltage and could be adjusted or supplied with a different regulator depending on 

each application needs 

Power Rail of 

i.MX50 

NVCCSRTC 32 kHz osc. power 

(when chip off) 

VCC LP Transistor 

power 

VDDA Peripheral 

Memory + L2 

Cache power 

Table 9. i.MX50 voltage domain supplies with the MC34709 

I.MX50 MC34709 

Power Domain MIN TYP MAX 

Associated 

Regulator 

PUM[4:0] 

=1110 

Curren 

t (mA) PUS 

1.2 VSRTC 1.2 - 

1.2 SW2 1.2 1000 0 

1.2 SW3 1.2 500 1 

VDDAL1 L1 Cache power 1.2 SW3 1.2 500 1 

VDDGP Core and G 

Transistor power 

VDDO2P5 Predriver for EMI 

pads 

1 SW1A/B 1 1600 2 

2.5 VDAC 2.5 50 3 

NVCC_EMI_DRAM Power to EMI pins 1.2 SW4B 1.2 500 4 

VREF DRAM Reference 0.9 

ALL 3.3V IO NVCC 3.0 V I/Os - 

VDD3P0 VDD2P5 LDO 

input + power to 

Bandgap, 

DCDC predriver, 

tempsensor, 480 

MHz PLL 

USB_OTG_VDDA33 Power to USB 

Host 

USB_H1_VDDA33 Power to USB 

OTG 

All 1.8 IO NVCC 1.8 V I/Os - 

NVCC_RESET (LVIO) Power to 

POR_B,RESET_I 

N_B, 

TESTMODE, & 

BOOTMODE[0:1] 

3 SW4A 3.15 500 4 

3.3 VUSB 3.3 100 9 

3.3 VUSB 3.3 100 9 

1.875 or 

2.775 

SW5 1.8 1000 5 




Power Rail of 

i.MX50 

VDD2P5 Power to 24 MHz 

osc, efuse, xtalok, 

32 kHz osc. power 

mux 

USB_OTG_VDDA25 Power to USB 

Host 

USB_H1VDDA25 Power to USB 

OTG 

2.5 VGEN2 2.5 250 6 

2.5 VGEN2 2.5 250 6 

2.5 VGEN2 2.5 250 6 

VDD1P8 Power to all PLLs 1.8 VPLL 1.8 50 7 

VDD1P2 Power to all PLL 

digital, 32 kHz osc. 

(when chip on), 

much of analog, 

digital 

Table 9. i.MX50 voltage domain supplies with the MC34709 

I.MX50 MC34709 

Power Domain MIN TYP MAX 

Associated 

Regulator 

PUM[4:0] 

=1110 

Curren 

t (mA) PUS 

1.2 VGEN1 1.2 250 8 



5.3.1 Interfacing Block Diagram 


The following block diagrams show all the power connections needed for the interface, as well as how the 

communication signals must be connected between the i.MX50 and MC34709. 

5.0V 

4.2V 

regulator 

VIN 

MC34709 

External 

DC/DC 

regulator 

SW1A/B 

SW2 

SW4 

VUSB 

SW5 

VPLL 

VGEN2 

VSW3 

VUSB2 

VDAC 

VSW4A 

VGEN1 

3.15 V 

VDDGP 

VCC 

USB_VDDA33 

VDD2P5 

VDDO25 

Figure 22. i.MX50 Power Interface with MC34709 Block Diagram 



i.MX50 

NVCC_EIM_DRAM 

POP_LPDDR2_18V 

NVCC_RESET 

NVCC_JTAG 

VDD1P8 

NVCC_KEYPAD 

(OPT) 

VDDA 

VDDAL1 

VDD3P0 

NVCC_MISC 

NVCC_SPI 

NVCC_SD1 

NVCC_SD2 

POP_NAND_VCC 

NVCC_NANDF 

NVCC_KEYPAD 

NVCC_SSI 

NVCC_UART 

NVCC_LCD 

NVCC_EPDC 

VDD1P2 

Peripherals 

CODEC 

HDMI 

ETHERNET 

3G PCIe 

RS-232


MC34709 

RESETBMCU 

RESETB 

STANDBY 

POWERON1 

WDI 

INT 

UID 

CKL 

MISO/SDA 

Figure 23. i.MX50 Control Interface with MC34709 Block Diagram 

5.3.1.1 3.15 V DC-DC power supply 

SWx 

POR_B 

WDOG 

CLK32MCU CLK 

PUMS1 

PUMS2 

PUMS3 

PUMS4 

PUMS5 

SWx 

SWx 

GPIOX_X 

i.MX50 

RESET_IN_B 

PMIC_STBY_REQ 

PMIC_ON_REQ 

USB_OTG_ID 

CSPI_SCLK 

CSPI_MISO/MOSI 

For system stability, it is recommended that you use an extra 3.15 V DCDC power supply to support large current 

requirements (for example a 3G module or Wi-fi card). The MC34709 has limited 3.15 V output ability to supply al 

peripherals, however, in cases where Ethernet, 3G, or Wi-fi are not required, this buck converter may be eliminated 

from the power three. 



VDC

5.3.2 Interface Power-up Sequence 

The resulting power-up sequence of the interface is shown in the following figure 

Peripherals 

CODEC 

HDMI 

ETHERNET 

3G PCIe 

RS-232 

VDDA 

VDDA1 

Figure 24. Power up Sequence Flow Chart 


VCC SW2 

VDDGP 

VDDO2P5 

VDD3P0 

NVCC_MISC 

NVCC_SPI 

NVCC_SD1 

NVCC_SD2 

POP_NAND_VCC 

NVCC_NANDP 

NVCC_KEYPAD 

NVCC_SSI 

NVCC_UART 

NVCC_LCD 

NVCC_EPDC 

POP_LPDDR2_18V 

NVCC_RESET 

NVCC_JTAG 

VDD2P5 

USB_VDDA25 

VDD1P8 

VDD1P2 

HDMI (perpheral) 

USB_VDDA33 



3.15V 

DC-DC 

regulator 

SW3 

SW1A/B 

VDAC 

SW4A 

SW4B 

VREFDDR 

SW5 

VGEN2 

VUSB2 

VPLL 

VGEN1 

VUSB


5.4 Application Example with the MC34709 

The following schematic is simplified application example for interfacing the MC34709 with an i.MX50 processor. 

note that this schematic only includes the block related to the power section as well as power management 

controlling signals. 

5_VGEN2 

DCDC_3V15 

3V15_SW4A_CPU 

VUSB2_2V5 2V5_VGEN2 

0 

R92 

R479 0 DNP 

1V8_VPLL 

0 

1V2_VGEN1 

0 

C95 

68uFDNP 

2V5_VGEN2 3V15_SW4A_CPU 

DNP 0 

C96 

DNP 

0.1UF 

GND 

3V15_SW4A_CPU 

3V15_SW4A_CPU 

3V15_SW4A_CPU 

3V15_SW4A 

3V15_SW4A_CPU 

R368 0.001 

0 

DNP 0 

R95 

R466 0 DNP 

3V15_SW4A_CPU 

SH12 

DNP 

3V15_SW4A_CPU 

3V15_SW4A_CPU 

3V15_SW4A_CPU 

R412 

C63 

R462 

0.1UF 

R499 

GND 

C68 

0.1UF 

VDD3P0 U5 

VDD3P0 

VDD2P5 V5 

VDD2P5 

R93 

C84 

GND 

C69 

VDD1P8 V6 

VDD1P8 

0.1UF 22UF 

GND 

C90 

VDD1P2 U6 

C91 

VDD1P2 

22UF 0.1UF 

GND 

1V8_SW5 

0 R463 

C76 

Not used (tied off to 1.8V) 

0.1UF 

VDD_DCDCI R7 

VDD_DCDCI 

R465 0 

GND 

GND 

C97 

0.1UF 

C110 

0.1UF 

C114 

0.1UF 

GND 

U6E 

GND 

DNP L10 

2 

2.2UH 

1 VDD_DCDCO T6 

VDD_DCDCO 

R6 

GND_DCDC 

H5 

NVCC_KEYPAD 

J5 

NVCC_MISC 

L5 

NVCC_UART 

i.MX50 - POWER 

GND 

C124 

0.1UF 

GND 

C118 

0.1UF 

C119 

0.1UF 

C120 

0.1UF 

C121 

0.1UF 

NVCC_EPDC 

C122 C123 

0.01UF 10UF 

3V15_SW4A_CPU 

3V15_SW4A_CPU 

GND 

GND 

3V3_USB 3V15_SW4A_CPU C125 

C127 

C126 

0.1UF 

USB_H1_VDDA33 

USB_3V3 R98 0 

22UF 

0.01UF 

GND 

C128 

0.1UF 

C129 

0.1UF 

GND 

PLace close to MX50 

C130 C131 

GND 

VUSB2_2V5 

0.1UF 0.1UF 

USB_2V5 

R100 0 

GND 

C133 

0.1UF 

C134 

GND 

1V2_RTC 

0.1UF 

NVCC_SRTC 

SH14 

DNP 

GND 

C136 

0.1UF 

GND 

3V15_SW4A_CPU 

NVCC_JTAG 

GND 

C137 

1V8_SW5 

0.1UF 

R459 0 

C138 

0.1UF 

GND 

1V8_SW5 3V15_SW4A_CPU 

NVCC_RESET 

GND 

C139 

0.1UF 

R461 0 DNP 

W11 

F9 

NVCC_EPDC1 F10 

NVCC_EPDC2 

F11 

NVCC_EPDC3 

F12 

NVCC_EPDC4 

P10 

NVCC_LCD 

P12 

NVCC_NANDF1 

USB_H1_VDDA25_1 

P5 

NVCC_SD2 

N5 

NVCC_SD1 

M5 

NVCC_SPI 

Y9 

USB_OTG_VDDA25_1 W9 

USB_OTG_VDDA33 Y11 

P11 

NVCC_NANDF2 

NVCC_SRTC R5 

K5 

NVCC_SSI 

NVCC_JTAG P9 

NVCC_RESET P6 

SH10 

DNP 

R99 0 DNP 

C132 

0.1UF 

C135 

0.1UF 

R101 0 DNP 

R460 0 

MCIMX508 

T7 

GND_KEL 

VSS1 

VSS2 

VSS3 

VSS4 

VSS5 

VSS6 

VSS7 

VSS8 

VSS9 

VSS10 

VSS11 

VSS12 

VSS13 

VSS14 

VSS15 

VSS16 

VSS17 

VSS18 

VSS19 

VSS20 

VSS21 

VSS22 

VSS23 

VSS24 

VSS25 

VSS26 

VSS27 

VSS28 

VSS29 

VSS30 

VSS31 

VSS32 

VSS33 

VSS34 

VSS35 

VSS36 

VSS37 

VSS38 

VSS39 

VSS40 

VSS41 

VSS42 

VSS43 

VSS44 

VSS45 

VSS46 

VSS47 

T5 

W5 

M6 

N6 

L7 

M7 

N7 

P7 

J8 

K8 

L8 

M8 

N8 

P8 

L9 

M9 

N9 

N10 

R10 

G11 

H11 

N11 

R11 

G12 

H12 

M12 

N12 

R12 

G13 

H13 

J13 

K13 

L13 

M13 

N13 

P13 

R13 

G14 

H14 

J14 

L14 

M14 

P14 

R14 

H15 

M15 

R15 

GND 

VDDGP 

VDDGP_1 G6 

VDDGP_2 H6 

J6 

VDDGP_3 

VDDGP_4 K6 

L6 

VDDGP_5 

VDDGP_6 G7 

VDDGP_7 H7 

J7 

VDDGP_8 

VDDGP_9 K7 

VDDGP_10 G8 

VDDGP_11 H8 

VDDGP_12 G9 

VDDGP_13 H9 

VDDGP_14 G10 

VDDGP_15 H10 

Figure 25. i.MX50 Voltage Domain Distribution 



VCC_1 K10 

L10 

VCC_2 

VCC_3 M10 

VCC_4 K11 

L11 

VCC_5 

VCC_6 M11 

J12 

VCC_7 

VCC_8 K12 

L12 

VCC_9 

VDDA_1 K9 

J11 

VDDA_2 

J9 

VDDAL_1 

J10 

VDDAL_2 

L17 

VDDO25 

NVCC_EMI_DRAM_1 K14 

NVCC_EMI_DRAM_2 N14 

NVCC_EMI_DRAM_3 J15 

NVCC_EMI_DRAM_4 K15 

NVCC_EMI_DRAM_5 L15 

NVCC_EMI_DRAM_6 N15 

NVCC_EMI_DRAM7 P15 

J16 


NVCC_EMI_DRAM10 K16 

NVCC_EMI_DRAM11 L16 

NVCC_EMI_DRAM12 M16 

NVCC_EMI_DRAM14 P16 


NVCC_EMI_DRAM8 H16 

NVCC_EMI_DRAM13 N16 

NC1 

NC2 

NC3 

NC4 

A1 

Y1 

A20 

Y20 

NVCC_EIM1 F6 

NVCC_EIM2 F7 

NVCC_EIM3 F8 

VCC 

VDDO2P5 

C64 C65 C66 C77 C78 C79 C80 C67 C81 C82 C83 

0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.01UF 0.01UF 10UF 22UF 

GND 

C70 C85 C71 C86 C87 C88 C72 C73 C89 

0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.01UF 0.01UF 10UF 22UF 

GND 

VDDA 

C74 C92 C93 C75 

0.1UF 0.1UF 0.1UF 0.1UF 

GND 

GND 

GND 

GND 

2V5_VDAC 

R370 0 

C94 

0.1UF 

JP3 

HDR 1X2 

DNP 

1 

2 

R96 0.001 

NVCC_EIM 

C111 C112 C113 C115 C116 C117 

SH8 

DNP 

0.1UF 0.1UF 0.1UF 0.01UF 0.01UF 10UF 

1V2_SW3 

JP1 

HDR 1X2 

DNP 

1 

2 

R94 0.001 

3V15_SW4A_CPU 

1V2_SW2 

NVCC_EMI_DRAM 

C98 C99 C100 C101 C102 C103 C104 C105 C106 C107 C108 C109 

0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.01UF 0.01UF 10UF 10UF 

JP2 

HDR 1X2 

DNP 

1 

2 

R91 0.001 

1V_SW1 

JP4 

HDR 1X2 

DNP 

1 

2 

R97 0.001 

1V2_SW4 

ICAP Classification: FCP: ___ FIUO: X PU 

Drawing Title: 

i.MX50 Reference Desig

1V8_SW5 

0.02 R367 

(PUS_6) C45 

22uF 

3V15_SW4A 

(PUS_5) 

GND 

SWBST 

C46 

22UF 

GND 

R369 0.02 

C38 

22UF 

GND 

GND 

(PUS_10) 

VCC_BP 

C252 

0.01UF 

C21 

10UF 

VREFDDR 

GND 

VCC_BP 

C20 

4.7uF 

BRL3225 L8 

2 

1 

VCC_BP 

VCC_BP 

VUSB2_2V5 

C28 

0.1UF 

GND 

GND 

SW5LX 

C18 

4.7uF 

GND 

VGEN1 has an internal PMOS pass FET and is powered from the SW5 buck 

for an efficiency advantage 

and reduced power dissipation in the pass devices. 

21 

2 

1 

F15 

SWBSTIN 

L9 

2.2UH 

G14 

SWBSTLX 

D6 

MBR120LSFT1G 

H15 

SWBSTFB 

C27 

0.1UF 

C19 

C26 

4.7uF 

0.1UF 

1V2_SW4B 

1V2_SW4B for EMI_DRAM_PAD 

GND 

BRL3225 L7 

(PUS_5) 

C39 

22UF 

2 

1 SW4BLX 

VCORE for Parallel Dual Phase Mode 

VCOREDIG for Parallel Single Phase Mode 

GND for separate independent output mode 

GND 

P4 

SW4AIN 

C25 

0.1UF 

2 

L6 

GND 

1 

SW4ALX 

BRL3225 

R3 

SW4ALX 

N2 

SW4AFB 

M6 

VCOREDIG 

DNP 0 R56 

SW4CFG 

DNP 0 R57 

VCORE 

0 R58 

0 

0 

R378 

C49 

1uF 

1V2_SW4B 

0.1UF C48 

VCC_BP 

Q8 

NSS12100XV6T1G 3 

R401 

1V8_SW5 

(PUS_9) 1.2V for PLL Digtal 1V2_VGEN1 

0 

4 

6 

5 

2 

1 

C51 

2.2UF 

P7 

SW5IN 

R8 

SW5LX 

M8 

SW5FB 

P5 

SW4BIN 

R6 

SW4BLX 

P2 

SW4BFB 

VUSB2DRV 

R373 

SWBST 

GND 

3V3_USB 

R65 0 

D1 

VINUSB 

(PUS_10) 

R375 0 

D2 

VUSB 

C52 

2.2UF 

0 

U3C 

C47 

0.1UF 

R365 

GND 

SWBST 

5.00, 5.05, 5.10, 5.15V 

380mA Boost 

SW5 

1.200-1.85V 

1000mA Buck 

SW4B 

1.200-1.85, 2.5, 3.15V 

500mA Buck 

SW4A 

1.200-1.85, 2.5, 3.15V 

500mA Buck 

U3B 

J14 

VINREFDDR 

VREFDDR 

K15 

VREFDDR 

0.6-0.9V 

10mA LDO 

J15 

VHALF 

P14 

VUSB2DRV 

R14 

VUSB2 

H14 

VINGEN1 

H12 

VGEN1 

C57 

2.2UF 

VUSB2 

2.5, 2.6, 2.75, 3.0V 

65mA INT. 

350mA EXT. PNP 

VGEN1 

1.2, 1.25, 1.3, 1.35, 

1.4, 1.45, 1.5, 1.55V 

250mA INT 

VUSB LDO 

3.3V 

100mA INT. 

MC34709 

SW1 

0.650-1.4375V 

2000mA Buck 

SW2 

0.650-1.4375V 

1000mA Buck 

SW3 

0.650-1.4375V 

500mA Buck 

MC34709 

Figure 26. MC34709 Power Supplies Schematic 


VPLL LDO 

1.2, 1.25, 

1.5, 1.8V 

N15 R363 0 

LDOVDD 

N14 VDACDRV 

VDACDRV 

VDAC P15 

L14 VGEN2DRV 

VGEN2DRV 

VGEN2 M15 

L4 BRL3225 

SW2LX 1 2 

Support source for VUSB2,VDAC and VGEN2 

VCC_BP 

GND 

Q10 


3 

2V5_VGEN2 Power for Keypad 

(PUS_7) 

R362 0 

For VDAC (Q9) For VGEN2(Q10) 

C30 C31 

(PUS_3) 

22UF 22UF 

VCOREDIG for Parallel Single Phase Mode 

VCORE for Parallel Dual Phase Mode 

1.8V for PLL Analog 

(PUS_8) 



PC34709VK 

50mA LDO 

VDAC LDO 

2.5, 2.6, 

2.7, 2.775V 

250mA 

VGEN2 LDO 

2.5, 2.7, 2.8, 2.9, 

3.0, 3.1, 3.15, 3.3V, 

50mA INT. 

250mA EXT. PNP 

PC34709VK 

L15 

VINPLL 

K14 

VPLL 

R9 

SW1ALX 

VCC_BP 

VCC_BP 

SW3LX 

VCC_BP VCC_BP 

GND 

P11 

SW1IN1 

P10 

SW1IN2 

R11 

SW1BLX 

P13 

SW1FB 

K10 

SW1PWGD 

L12 

SW1CFG 

B11 

SW2IN1 

A10 

SW2LX1 

A12 

SW2FB 

A13 

SW2PWGD 

E14 

SW3IN1 

D15 

SW3LX1 

B13 

SW3FB 

C55 

0.1UF 

GND 

3 

TP63 

R35 0 

C158 

2.2UF 

4 

1 

2 

5 

6 

4 

1 

2 

5 

6 

GND 

TP64 

GND 

VCC_BP 

GND 1V_SW1 

C17 

4.7uF 

1 2 

L5 BRL3225 

C58 

0.1UF 

C15 

4.7uF 

C59 

2.2UF 

C22 

0.1UF 

BRL3225 

1 2 

L3 

R36 0 DNP 

GND 

GND 

C24 

0.1UF 

GND 

C16 

4.7uF 

VCOREDIG 

1V8_VPLL 

R366 0 

VCC_BP 

GND 1V2_SW2 

VCC_BP 

C23 

0.1UF 

GND 

C33 

22UF 

GND 

C35 

10UF 

(PUS_1) 

1V2_SW3 

(PUS_2) 

VCC_BP 

C50 

Q9 


2.2UF 

GND 

2V5_VDAC 2.5V for VDDO2P5 (EMI PADS) 

R364 

C53 

2.2UF 

0 

(PUS_4)


C3 

22UF 

R1 0 

3V15_SW4A 

GND 

VSOURCE 

R8 0 DNP 

R475 

332K 

DCDC_3V15_EN 

3.15V/2A Regulator 

R78 

0 

GND 

R474 

13K 

J84 

5 

U30 

PVDD 

1 

2 HDR 1X2 

GND 

C290 

1000PF 

6 

Vout = 3.15V for R1=294K, R2=100K 

Vout = 0.8v* (R(out-fb) / R(fb-gnd) + 1) 

Figure 27. 3.15V DC-DC Regulator 

Figure 28. Main BP Supply (Battery or 4.2V) 



VDD 

LX 3 

FB 7 

8 

COMP 

2 

PGND 

GND 

4 

1 

SHDN/RT 

PAD 9 

Battery Regulator & Terminals 

J1 

L13 

1 2 

2.2uH 

R1 

R2 

GND 

R2 

294K 

C2 

22UF 

R3 

100K 

DCDC_3V15 

3-pin connector J2 allows the use of aftermarket Li-ION batteries. Recommended battery 

capacity is 800 - 1500 mAh. 

2 

1 

B2B-PH-K-S 

+ 

- 

THERM 

BATT 

GND 

Silkscreen Labels: 

+ 

- 

THERMISTOR 

5V_MAIN U2 

REG_4V2 

C7 

SH1 

DNP 

2 

1 

IN 

EN 

NR/FB 

R1 

C6 

20PF C5 

10UF 

10UF 

TPS78601 

5 

3 

6 

OUT 

GND 

GND_TAB 

4 

R4 

42.2K 

GND 

J2 

3 

2 

1 

CON_1X3 

DNP 

3 

2 

1 

J3 

HDR_1X3 

BATT_NTC (pg6) 

Vout = 1.2246 * [ R(out-fb) / R(fb-gnd) + 1 ] 

Vout = 4.19V for R1=42.2K, R2=17.4K 

R2 

R7 

17.4K 

VCC_BP 

C4 

47uF 

GND 

3 

2 

1 

HDR_1X3 

J4

Sensitive analog lines. 

X1-X2 and Y1-Y2 

make differential pairs. 

(pg17) 

(pg17) 

(pg17) 

(pg17) 

1.75V~3.6V 

SPI: Hold low when cold start 

I2C: Hold high when cold start. 

(pg9) 

(pg12,9) 

(pg12,9) 

(pg12,9) 

VCOREDIG VCORE R34 0 DNP 

1.5V 

2.775V 

1.2V 

Coin cell. 

TOUCH_X0 

TOUCH_X1 

TOUCH_Y0 

TOUCH_Y1 

CSPI_SS0 

CSPI_SCLK 

CSPI_MISO 

CSPI_MOSI 

C40 C41 C42 

0.1UF 1uF 1uF 

3 2 

1 

GND 

- 

+ 

0 

1 

0 

GND 

BT1 

2994TR 

TP1 

DNP 

GND 

PUMS5 

PUMS4 

PUMS3 

PUMS2 

PUMS1 

1 ADIN9 

GND 

C159 C161 

0.1UF 1uF 

R49 0 

R48 0 

R51 0 

R52 0 

R54 4.7K 

C44 

0.01UF 

GND 

GND 

QZ1 

1 2 

C32 2.2UF 

3V15_SW4A 

GND 

VCOREDIG 

VCORE 

REFCORE 

32.768KHZ 

C61 

C62 

15pF 

15pF 

U3D 

Power Up Mode 

R29 

0 

DNP 

R37 

0 

R46 

0 

C56 

0.1UF 

R27 

0 

R38 

0 

DNP 

H6 

ADIN9 

J5 

ADIN10 

J6 

ADIN11 

K6 

TSREF 

K5 

TSX1/ADIN12 

L4 

TSX2/ADIN13 

L6 

TSY1/ADIN14 

L3 

TSY2/ADIN15 

A4 

SPIVCC 

B2 

CS 

B1 

CLK 

A2 

MISO 

B3 

MOSI 

L1 

VDDLP 

J1 

VCOREDIG 

J2 

VCORE 

K1 

VCOREREF 

M2 

LICELL 

G1 

XTAL2 

E1 

XTAL1 

VCOREDIG 

GND 

R30 

0 

R39 

0 

DNP 

R31 

0 

R40 

0 

DNP 

SUBSREF 

SUBSANA1 

SUBSANA2 

SUBSLDO 

SUBSGND 

SUBSPWR 

SUBSPWR3 

SUBSPWR2 

SUBSPWR1_8 

SUBSPWR1_7 

SUBSPWR1_6 

SUBSPWR1_5 

SUBSPWR1_4 

SUBSPWR1_3 

SUBSPWR1_2 

SUBSPWR1_1 

U3A 

R32 

0 

DNP 

R41 

0 

K8 

K12 

F10 

H10 

J8 

K9 

G10 

E11 

J9 

H9 

H8 

G9 

G8 

F9 

F8 

E8 

H5 

GNDADC 

GND GND 

General 

Purpose ADCs 

Touch Screen 

Interface 

SPI/I2C 

Interface 

Reference 

Generation 

Coincell 

Battery Backup 

Crystal 

Oscillator 

(pg10,6) 

(pg10,6) 

GNDSPI 

GNDCORE 

GNDREF 

GNDUSB 

GNDGPIO 

GNDRTC 

GNDCTRL 

A3 

H1 

M1 

C1 

C9 

F1 

B6 

STANDBY 

PMIC_STBY_REQ 

1.2V level input 

GND 

PMIC_STBY_REQ 

MC34709 

R53 

10K 

GNDREG1 

GNDREG2 

GNDREF1 

GNDREF2 

M14 

J12 

N9 

B12 

1V2_RTC 

1 

VCCA 

2 

A 

GND 

3 

GND 

GND 

6 

VCCB 

R55 0 DNP 

F14 

PC34709VK 

C36 

0.1UF 

P8 

1V8_SW5 

R45 0 

GND 

4 

B 

NC 5 

U4 

NLSV1T34 

C37 

0.1UF 

GNDSWBST 

GNDSW5 

GNDSW4B 

GNDSW4A 

GNDSW1A1 

GNDSW1B1 

SW1VSSSNS 

GNDSW2 

P6 

P3 

P9 

P12 

R13 

B10 

USB/Audio 

Control Logic 

PC34709VK 

R50 0 

(active high) 

STANDBY 

Figure 29. MC34709 System/Control Signals 


R89 0 open drain output 

R88 0 (active low) 

High: ICTEST mode 

Low: normal mode 

R75 

0 

DNP 



D14 

GNDSW3 

A8 

PWM1 

A7 

PWM2 

GND 

BP N1 

R1 

NC_1 

A14 

NC_2 

B15 

NC_3 

3 

R76 0 

3V15_SW4A 

PWNON1 

PWRON2 

PUMS1 

PUMS2 

PUMS3 

PUMS4 

PUMS5 

R80 

100K 

(pg10) 

GND 

GLBRST 

RESETBMCU 

RESETB 

VCC_BP 

R28 

C14 

0 

10UF 

MBR120LSFT1G 

LICELL A C 

D15 

U10 

NCP4682 

D14 

GND 

3 

CE 

4 

1 

VOUT 

A C VDDLP 

BP A C C291 

VIN 

MBR120LSFT1G 

D16 

0.1UF 

C292 

MBR120LSFT1G 

0.1UF 

0 

0 

0 

C8 

GPIOVDD 

R72 0 

1V8_SW5 

C7 

GPIOLV0 

B7 

GPIOLV1 

B9 

GPIOLV2 

GPIOLV1 R77 0 

E10 

GPIOLV3 

GPIOLV4 R82 0 

Output, 0~SPIVCC 

E3 

CLK32K 

G3 

CLK32KMCU 

F3 

CLK32KVCC 

H2 

VSRTC 

K3 

WDI 

B5 

RESET 

D5 

RESETBMCU 

B4 

INT 

P1 

STANDBY 

A5 

GLBRST 

A6 

PWRON1 

E5 

PWRON2 

PUMS1 G6 

D6 

SDWN 

PUMS2 G5 

F6 

PUMS3 

F5 

PUMS4 

E6 

PUMS5 

A9 

ICTEST 

SW2 

1 

4 2 

SPST PB 

3V15_SW4A 

JTAG_RESET_B 

Output, 0~1V2_RTC 

VCOREDIG 

GND 

VCOREDIG 

R66 

10K 

GND 

R73 0 

C249 

0.1UF 

VSRTC WORKAROUND 

RESET 

1.8V logic level 

Input, 0~3.6V 

R85 0 Output, 0~SPIVCC 

PMIC_INT(GP4_18) (pg9) 

R84 0 (active high) STANDBY Input, 0~3.6V, high level (1.0~3.6V) 

R83 0 

GLBRST Input, 0~VCOREDIG(1.5V) 

GLBRST 

1V2_RTC 

GLBRST (pg17) 

PWM1 (pg10) 

ECKIL (pg10) 

GND 

3V15_SW4A 

U20 

1V8_SW5 

5 

1 

VCC 

10K 

R90 

DNP 

R79 

10K 

R74 

0 

C54 

0.1UF 

DNP 1 

DNP 1 

R87 0 

R397 0 2 

4 

R67 0 DNP 

TP6 

TP7 

2 

5 GND 

TAB_GND 

3 

GND 

NC7SP125P5X 

R70 0 

D13 

BAT54A-7-F 

R71 0 1 

3 

2 

1V8_SW5 

R68 

68K 

RESETB 

RESETBMCU 

GND 

3V15_SW4A 

R69 

68K 

R454 

10K 

R86 0 

GND 

WDOG_B (pg9) 

SYSTEM_DOWN(GP4_17) (pg9) 

POR_B (pg10) 

RESET_IN_B (pg10) 

C60 

0.1UF


(pg6) POR_B 

RESET_IN_B 

(pg6) 

(pg10) BOOT_MODE0 

(pg10) BOOT_MODE1 

R128 

10K 

(pg6) 

GND 

PMIC_STBY_REQ 

(pg6) PMIC_ON_REQ 

C140 

18PF 

DNP 

(pg6) 

QZ2 

1 

2 

32.768KHZ 

DNP 

GND 

ECKIL 

C141 

18PF 

DNP 

U6C 

Y5 

POR_B 

V3 

U3 

BOOT_MODE0 

BOOT_MODE1 

RESET_IN_B 

W3 

U4 

TEST_MODE 

W4 

ECKIL 

CKIL 

Y2 

Y3 PMIC_STBY_REQ 

PMIC_ON_REQ 

Y4 

SH22 

DNP 

MCIMX508 

i.MX50 - CONTROL PINS 

NVCC_RESET 

NVCC_RTC 

NVCC_JTAG 

JTAG_TCK R8 

JTAG_TMS R9 

JTAG_TDI U8 

JTAG_TDO T9 

JTAG_TRSTB U7 

JTAG_MOD T8 

CKIH V4 

XTAL Y6 

EXTAL W6 

Figure 30. i.MX50 Control Signals 

If an external battery charger is required, it is recommended to use a charger with power path management which 

isolates the battery from the system node while charging. The main system voltage from the charger will be 

connected directly to the BP node while the external charging voltage and the battery are connected on the charger’s 

end. 



GND 

JTAG_TCK (pg10) 

JTAG_TMS (pg10) 

JTAG_TDI (pg10) 

JTAG_TDO (pg10) 

JTAG_TRST_B (pg10) 

SH21 DNP 

JTAG_MOD 

1V8_SW5 

R119 

10K 

DNP 

R129 

1K 

GND 

1V8_VPLL 

Y2 

OSC. 

Y1 

VCC 

4 GND 

1 

3 

2 

10K R134 C142 

GND 

24MHZ 

C144 

15pF 

C143 

15pF 22.5792MHZ 

DNP 

0.1UF 

GND 

GND 

4 

3 

OUT 

DGND 2 

EN/DIS 1 

R130 1.0M

5.5 MC34709 layout example 


The following is a layout example of the MC34709 implemented on a four layer board with all component on the top 

layer and using standard 8 mils vias. 

S3 

S4 

BH1 

L12 

R153 

BH4 

S1 

F1 

J123 

C95 

C93 

R155 

R154 

TP1 

C94 

1 

R135 

R137 

5 

J121 

S2 

1 

5 

+ 

4 

U7 

3 

C92 

C91 

5 1 

C89 C87 

R132 C88 

C A 

D17 

1 

1 

2 

6 

R152 

L11 

J125 

C86 

C67 

R165 

1 Y2 2 

C85 

R164 

R157 

C83 

C82 

R158 R159 

24 C81 

25 

U6 

C90 

36 

37 R131 48 

4 3 

1 

13 

12 

+ 

+ 

2 

1 

+ 

R147 

R146 

R148 

R149 

R144 

C78 

C68 

R151 

C84 

C80 

R163 

R162 

R160 

R161 

4 U3 5 

C79 

R145 

R156 

J124 

R134 

C70 

4 U2 5 

BH5 

R58 

R127 

C41 

D25 

C A 

R133 

C69 

J122 

C72 

2 

1 

D20 

C A 

1 8 

4 U4 5 

SW1 

R138 C77 

R139 C73 

C 

A 

D23 

A 

D18 

A 

D19 

A 

D24 

A 

D22 

A 

D21 

R136 

C71 

SW2 

2 2 

C61 

C64 

R66 R67 

R52 

C 

R141 

C 

R142 C75 

C 

R140 C76 

C 

R143 C74 

C 

SW3 

L4 

R122 

C33 

R16 

R15 

R51 

R14 

R59 

R126 

16 

1 

SW5LX1 

R45 

PWM2 

GNDSW1A1 

R39 

R32 

PWRON1 

C57 

TSREF1 

Figure 31. KIT34709VKEVBE FAB Drawing 



12 

11 

D5 

Q8 

1 

PWM1 

C8 

TSY1 

R36 

C 

1 

J60 

1 

R46 

SW2LX1 

R121 C62 

R130 

R57 C60 

R55 

GNDSW5 

A 

J68 

A 

R31 

R34 

SW1FB1 

D3 

C53 

D4 

J62 

1 

C7 

9 

8 

C 

R33 

Q7 

C34 

C26 

C14 

1 

1 

J67 J74 

1 1 

J66 

C45 

C29 

J3 

TP_XTAL2 

RESETBMCU1 

VCOREDIG1 

REFCORE1 

VDDLP1 

STANDBY1 

R150 

GLBRST1 

U5 

SW4 

J25 J65 

J29 

PWRON2 

J40 J64 

INT1 

J31 J30 

GNDSW2 VUSB1 

C50 C38 

Y1 C39 

R64 

R65 

C49 

C23 

C46 

C22 

C21 

C20 D11 C58 

L7 

R53 

D12 

TSY2 

CLKVCC1 

J58 J69 

J37 

L8 L9 

C16 

SW4ALX1 

C19 

GNDSWBST1 

C25 

SW4BLX1 

R125 

R60 

BAT1 

J81 

R42 

TSX2 

TSX1 

J80 J70 

D13 

R56 

R129 

C11 

D9 R48 

U1 

R49 

C9 

J78 

J71 J73 

C27 

A 

C 

ADIN9 

1 1 

ADIN11 

2 

5 4 

1 3 

1 

1 1 

1 

A 

1 2 1 

5 6 

SW2FB1 

SW3LX1 

GNDSWBST2 

1 1 

SW3FB2 

SWBSTLX1 

L5 

1 

R47 L10 

GNDSW4A1 

D10 

C6 

C66 

1 

1 

GNDSW3 

BA 

1 

D16 

R124 

DC 

C59 

J21 

F 

E 

C28 

HG C3 

C32 

1 

KJ 

1 

C40 Q3 C30 

M L 

P 

N 

C31 

C44 Q4 

VGEN2 VHALF1 

R 

VREFDDR1 

D7 C37 

VDAC1 

C15 

1 

D8 

C13 

LDOVDD1 

1 1 

1 2 

B 

B 

1 1 

1 

2 

1 

C 

2 

VUSB2 

GNDSW4B1 

1 

Q6 J52 

1 

Q5 

1 

J56 

1 

5 6 

R128 

VPLL1 

J32 

1 

Q2 

1 J43 

1 

Q1 

1 

J47 

1 

J79 

J77 

1 

1 

1 R41 

R44 

R43 

R40 

1R38 

1 

SW1ALX1 

L2 

SW1BLX1 

C 

L3 

J76 

R35 

R37 

J72 

1 1 1 1 1 

2012 FREESCALE 

KIT34709VKEVBE 

S/N 

700-XXXXX REV X 

SCH-XXXXX REV X 

16 

15 

1 

8 

5 

6 

1 

1 

2 

8 

STANDOFFS REQUIRED 

A 

ADIN10 

WDI1 

J2 

TP_XTAL1 

VCORE1 

GNDSW1B1 

BP_SENSE1 

VSRTC1 

VSWBST_SENSE1 

1 

J120 

1 

20 

2 

BH6 

19 

J118 

BH2 

BH3 

19 

2 

J117 

20 

1


Figure 32. KIT34709VKEVBE Top Layer 



Figure 33. KIT34709VKEVBE Layer 2 





Figure 34. KIT34709VKEVBE Layer 3 



170-27338 REV A 

Figure 35. KIT34709VKEVBE Bottom Layer 





5.6 Migrating from MC34708 to MC34709 

For customers migrating from the MC34708 platform to the MC34709 a very low design effort is required due to the 

high compatibility system between the to devices. Table 10 shows the main difference between both power 

management devices. 

Control Logic 

Table 10. MC34708 and MC34709 difference 

Features MC34708 MC34709 

• Power control logic with processor interface and event detection Yes Yes 

• Single SPI/I2C bus for control & register access Yes Yes 

• Real time clock and crystal oscillator circuitry with coin cell backup Yes Yes 

• Support for external secure real time clock on a companion system 

processor IC 

10 bit ADC 

Yes Yes 

• 4 wire resistive touchscreen interface Yes Yes 

• 7 External ADC inputs. Yes Yes 

• Dedicated ADC channel for Battery voltage sensing Yes No 

• Dedicated ADC channel for battery current sensing Yes No 

• Dedicated ADC channel for BP voltage Yes No 

• Dedicated ADC channel for Die temperature Yes Yes 

• Dedicated ADC channel for VBUS voltage. (USB device detection) Yes No 

• Dedicated ADC channel for coin cell voltage Yes Yes 

Power Supplies (10) 

• 5 Buck regulator Yes Yes 

• 1 Boost regulator Yes Yes 

• 8 LDO Regulators with internal and external pass devices. Yes Yes 

Auxiliary Circuits 

• USB/UART/Audio switching for mini-micro USB connector Yes No 

• Four general purpose low voltage I/Os with interrupt capability Yes Yes 

• Two PWM outputs Yes Yes 

• Two General purpose LED drivers Yes No 

Package 

• 206 MAPBGA - 8.0 x 8.0 mm - 0.5 mm pitch Yes No 

• 206 MAPBGA - 13 x 13 mm - 0.8 mm pitch Yes No 

• 130 MAPBGA - 8.0 x 8.0 mm - 0.5 mm Pitch No Yes 

Notes: 

10. All Power supplies have the same voltage and current rating on both devices. 



References 

Firmware portability is straights forward, since register maps are bit to bit compatible. However, the MC34709 uses 

a reduced set of register which eliminate all registers/bits related to the functionality not supported on the MC34709, 

therefore care must be taken that RESERVED registers/bits are not addressed on the firmware when porting the 

application to the MC34709. 

6 References 

Document 

Number 

Description Description / URL 

MC34709 Data Sheet http://cache.freescale.com/files/analog/doc/data_sheet/MC34709.pdf?fsrch=1&sr=2 

MC13892 Data Sheet http://cache.freescale.com/files/analog/doc/data_sheet/MC13892.pdf?fsrch=1&sr=1 

IMX50SDG Development Guide http://cache.freescale.com/files/32bit/doc/user_guide/IMX50SDG.pdf?fsrch=1&sr=1 

IMX50RM Reference Manual http://cache.freescale.com/files/32bit/doc/ref_manual/IMX50RM.pdf?fsrch=1&sr=10 

IMX50CEC Data Sheet http://cache.freescale.com/files/32bit/doc/data_sheet/IMX50CEC.pdf 



Revision History 

7 Revision History 

Revision Date Description of Changes 

1.0 12/2012 • Initial release 



Revision History 



How to Reach Us: 

Home Page: 

freescale.com 

Web Support: 

freescale.com/support 

Document Number: AN4603 

Rev. 1.0 

12/2012 

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© 2012 Freescale Semiconductor, Inc.

AN4603 - Freescale Semiconductor

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