TECHNOLOGY - Power Electronics
TECHNOLOGY - Power Electronics
TECHNOLOGY - Power Electronics
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<strong>TECHNOLOGY</strong><br />
®<br />
FOR DESIGNERS AND SYSTEMS ENGINEERS<br />
Smart<br />
SMPS Board<br />
Layout<br />
Cuts EMIp.8<br />
A PENTON PUBLICATION<br />
www.powerelectronics.com<br />
JANUARY 2013<br />
Vol. 39, No. 1
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
Efficiency (%)<br />
MULTI-PHASE<br />
IR3553<br />
4 x 6 mm - 40 A<br />
30<br />
DC-DC<br />
CONTROLLER<br />
29<br />
28<br />
27<br />
IR3551<br />
5 x 6 mm - 50 A<br />
26<br />
7 8 9 10 12 13 14<br />
25<br />
High Effi ciency, High Density<br />
PowIRstage <br />
24<br />
23<br />
IR3550<br />
6 x 6 mm - 60 A<br />
22<br />
PowIRstage ® footprint compatibility offers fl exible design<br />
21<br />
20<br />
Output Current (A)<br />
Scalable Solutions for Multi-Phase <strong>Power</strong> Systems<br />
PowIRstage ® offers exceptional effi ciency across the entire load range<br />
19<br />
18<br />
17<br />
16<br />
for more information call 1.800.981.8699 or visit us at www.irf.com<br />
60<br />
V out<br />
4mm<br />
6mm<br />
6mm<br />
6mm<br />
5mm<br />
Key Features<br />
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THE POWER MANAGEMENT LEADER
Here’s the latest in our growing family of high power, high performance LED drivers designed to simplify power delivery to high<br />
brightness LEDs. The LT ®<br />
3791’s 4-switch buck-boost controller topology operates from input voltages above, below or equal to<br />
the output voltage while delivering constant currents from 1A up to tens of amps. The LT3791 also provides ±4% LED current<br />
accuracy and ±1.5% output voltage accuracy to ensure the highest performance LED solutions.<br />
Part<br />
Number<br />
LT3741<br />
LT3743<br />
LT3755<br />
LT3756<br />
LT3791<br />
LED Drivers<br />
V IN Range (V)<br />
6 to 36<br />
6 to 36<br />
4.5 to 40<br />
6 to 100<br />
4.7 to 60<br />
100W+, 98% Efficient<br />
Buck-Boost LED Driver<br />
V IN<br />
Input<br />
Current<br />
Monitor<br />
Output<br />
Current<br />
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SHORTLED<br />
OPENLED<br />
Analog<br />
Dimming<br />
PWM Dimming<br />
Topology<br />
Synchronous<br />
Step-Down<br />
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Step-Down<br />
Multitopology<br />
Multitopology<br />
4-Switch Synchronous<br />
Buck-Boost<br />
R IN Single Inductor<br />
V IN<br />
LT3791<br />
TG1<br />
BG1<br />
BG2<br />
TG2<br />
PWMOUT<br />
GND<br />
4.7VIN to 60VIN, Short Circuit Proof with LED Protection & Diagnostics<br />
Comments<br />
LED Current up to 20A<br />
LED Current up to 40A with<br />
Fast LED Current Transitions<br />
V OUT up to 75V<br />
V OUT up to 100V<br />
V OUT from 0V to 60V with<br />
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R SENSE<br />
R LED<br />
Info & Free Samples<br />
www.linear.com/products/LEDdrivers<br />
1-800-4-LINEAR<br />
, LT, LTC, LTM, Linear Technology and the Linear logo are<br />
registered trademarks of Linear Technology Corporation. All other<br />
trademarks are the property of their respective owners.
CoverStory<br />
p.8<br />
Layout <strong>Power</strong> Supply Boards To<br />
Minimize EMI: Part 1<br />
By CHRISTIAN KUECK, Linear Technology<br />
PC-board layout sets the functional, electromagnetic<br />
interference (EMI), and thermal<br />
behavior of a power supply. Good layout from<br />
fi rst prototyping on actually saves signifi cant<br />
resources in EMI fi lters, mechanical shielding,<br />
EMI test time and PC board runs.<br />
COVER ART: Kamil Wierciszewski<br />
FOR DESIGNERS AND SYSTEMS ENGINEERS<br />
www.powerelectronics.com<br />
JANUARY 2013 • Vol. 39, No. 1<br />
DESIGN FEATURES<br />
eGaN® FET- Silicon <strong>Power</strong><br />
16 Shoot Out Volume 12:<br />
Optimizing Dead Time<br />
This volume of the eGaN FET-Silicon<br />
power shoot-out series looks at the impact<br />
of dead-time on system effi ciency<br />
for eGaN FETs and MOSFETs.<br />
Limitations of Traditional<br />
22 Circuit Protection for High<br />
Energy Surge Threats<br />
New transient current suppressors utilize<br />
high-speed, bidirectional, low resistance,<br />
compact current limiting devices to protect<br />
circuits from overcurrent surges.<br />
Ripple Generating Circuit<br />
27 for Constant-On-Time<br />
Controlled Buck Converters<br />
A systematic approach optimizes the<br />
ripple generating circuit to meet stability<br />
criteria and maintain accurate DC<br />
regulation.<br />
Intelligent <strong>Power</strong> Switches<br />
31 For 24 V Vehicle Systems<br />
A family of smart high side devices<br />
for 24V applications are compatible in<br />
footprint and software to address loads<br />
from 1 A to 12 A DC.<br />
Gate<br />
Drain<br />
GaN on<br />
Silicon<br />
HEMT<br />
Si<br />
MOSFET<br />
Interconnector<br />
CURRENT TRENDS<br />
2 <strong>Power</strong> <strong>Electronics</strong> Technology | January 2013 www.powerelectronics.com<br />
Bottom<br />
Substrate<br />
Si Die<br />
GaN Die<br />
Top Cap<br />
Source<br />
Substrate<br />
(a) (b) (c)<br />
PET INNOVATIONS<br />
35 GaN-on-Silicon-based<br />
<strong>Power</strong> Switch In Sintered,<br />
Dual-side Cooled Package<br />
Gallium Nitride (GaN) devices provide<br />
multi-kilowatt switching for electric<br />
vehicle traction or auxiliary power applications.<br />
j<br />
DEPARTMENTS<br />
3 EDITOR’S VIEWPOINT<br />
4 INDUSTRY HIGHLIGHTS<br />
39 NEW PRODUCTS<br />
40 ADVERTISER INDEX<br />
Drain<br />
Gate<br />
Source
EDITOR’Sviewpoint<br />
Basics of<br />
Electronic Components<br />
WANT TO know the details about a specific<br />
electronic component? “Encyclopedia<br />
of Electronic Components Volume 1” is<br />
the first book of a three-volume set that<br />
contains key information on electronics<br />
parts--complete with photographs, schematics, and diagrams.<br />
You’ll learn what each one does, how it works, why<br />
it’s useful, and what variants exist. In fact, author Charles<br />
Platt, notes that the encyclopedia serves two categories of<br />
readers: “the informed and the not-yet-informed.”<br />
“Encyclopedia of Electronic Components Volume<br />
1” puts reliable, fact-checked information right at your<br />
fingertips--whether you’re refreshing your memory or<br />
exploring a component for the first time. Beginners will<br />
quickly grasp important concepts, and more experienced<br />
users will find the specific details their projects require.<br />
For example, the first section is Battery:<br />
• What it does<br />
• How it works<br />
• Variants<br />
• Values<br />
• How to use it<br />
• What can go wrong<br />
A similar format is used for other components from<br />
Switches to Field Effect Transistors in 264 pages.<br />
No matter how much you can remember about a<br />
component, you’ll find details you’ve probably forgotten.<br />
Remember the unijunction transistor? A schematic and<br />
the associated text describe how to use it. And, under<br />
“What can Go Wrong” it points out an incorrect bias and<br />
overload.<br />
Engineers still use bipolar transistors, which are included<br />
in the book. The book notes that, “A bipolar NPN transistor<br />
consists of a thin central P-type layer sandwiched<br />
between two thicker N-type layers. The three layers are<br />
referred to as collector, base, and emitter, with a wire or<br />
contact attached to each of them.” Under “What Can Go<br />
Wrong,” it points out in a detailed explanation:<br />
• Wrong Connections on a Bipolar Transistor<br />
• Wrong Connections on a Darlington Pair chip<br />
• Soldering Damage<br />
• Excessive Current or Voltage<br />
• Excessive leakage<br />
A subject that readers of <strong>Power</strong> <strong>Electronics</strong> Technology<br />
should be familiar with is Voltage Regulators. The book covers<br />
only linear regulators. Under “What Can Go Wrong” are:<br />
• Inadequate Heat Management<br />
• Transient Response<br />
• Misidentified Parts<br />
• Misidentified Pins<br />
• Dropout Caused by Low Battery<br />
• Inaccurate Delivered Voltage<br />
Other types of power supplies are described in sections<br />
under “AC-DC <strong>Power</strong> Supply” and “DC-DC Converter.”<br />
For AC-DC <strong>Power</strong> Supply,” What can Go Wrong” includes:<br />
• High Voltage Shock<br />
• Capacitor Failure<br />
• Electrical Noise<br />
• Peak Inrush<br />
For DC-DC Converter, “What Can Go Wrong” lists<br />
the details of:<br />
• Electrical Noise in the Output<br />
• Excess Heat with No Load<br />
• Inaccurate Voltage Output with No Load<br />
I’m sure that many readers of <strong>Power</strong> <strong>Electronics</strong><br />
Technology could add several other possibilities to “What<br />
Can Go Wrong.” However, the format that Charles Platt<br />
uses is a good one and he uses it throughout the book.<br />
If you have a child who wants to become an electronics<br />
engineer, this would be a good book to read. Also, there<br />
is information in the book that you probably won’t find in<br />
any university courses.<br />
At the end of the book is a three-page listing of schematic<br />
symbols followed by a detailed 10-page index.<br />
Price of Volume 1 of the Encyclopedia is $24.99 (US)<br />
and $26.99 (Canada). Volume 1 covers power, electromagnetism<br />
and discrete semiconductors. Volume 2 will<br />
include integrated circuits and light and sound sources.<br />
Volume 3 will cover a range of sensing devices.<br />
SAM DAVIS, Editor-in-Chief<br />
www.powerelectronics.com January 2013 | <strong>Power</strong> <strong>Electronics</strong> Technology 3
INDUSTRY<br />
Professor Harvests Energy from Railroad Tracks<br />
STONY BROOK UNIVERSITY PROFESSOR<br />
LEI ZUO invents products to generate<br />
electricity from vibrations all around<br />
us. He has licensed technology to a California<br />
company for an automotive shock absorber<br />
that produces wattage from bumpy roads. He<br />
designed a contraption to derive electricity<br />
from swaying skyscrapers. And he built a<br />
device that harnesses the rumble of<br />
passing trains to power crossing gates<br />
in the middle of nowhere.<br />
The global market for such devices<br />
is expected rise to $5 billion in the<br />
next decade, says market research<br />
firm IDTechEx. Long Island officials<br />
are banking that developments<br />
by Zuo and his fellow researchers at Stony<br />
Brook, Brookhaven National Laboratory and<br />
other institutions will spur new technology<br />
companies to fill the vacuum left by the<br />
region’s waning aerospace industry.<br />
Zuo’s idea for powering railroad gates<br />
came while riding a train to Albany. As<br />
the rolling hills of the Hudson Valley<br />
flashed by out the window, Zuo felt his<br />
seat vibrate. Bells clanged at a crossing,<br />
and red lights flashed. Something inside<br />
Zuo clicked.<br />
Back at his lab, Zuo designed a roughly<br />
2-foot-long device that could be mounted<br />
on a railroad track. The vibrations of passing<br />
trains would set in motion a series of gears,<br />
turning the generator’s crank. Zuo calculated<br />
it could produce as much as 200<br />
watts: enough to power crossing<br />
gates and lights. He has approached<br />
the Metropolitan Transportation<br />
Authority about testing the device,<br />
but the agency has not committed.<br />
Zuo’s first significant energy<br />
harvesting success was the shock<br />
absorber, which he says generates as much<br />
as 400 watts on a smooth highway. Add<br />
potholes, and the potential output jumps<br />
above 1,600 watts. All told, the device<br />
can take enough strain off the battery and<br />
alternator to boost fuel efficiency by 2 to<br />
8 percent at 60 miles per hour, Zuo said.<br />
licensed the technology to Harvest Energy<br />
Inc., of Newport Coast, Calif.<br />
Fuel Cells For Residential, Commercial and Military <strong>Power</strong><br />
A<br />
NEW TECHNICAL MARKET RESEARCH REPORT, Fuel Cells For Residential, Commercial, And<br />
Military <strong>Power</strong>(FCB037A), from BCC Research, the global residential, commercial, and military<br />
fuel cell market was valued at $439 million in 2011 and should reach nearly $569 million in<br />
2012. Total market value is expected to reach nearly $1.7 billion in 2017 after increasing at a five-year<br />
compound annual growth rate (CAGR) of 24.2%.<br />
The market for fuel cell types can be broken down into three applications: solid oxide fuel cells<br />
(SOFCs), polymer electrolyte membrane fuel cells (PEMFCs), and other FCs.<br />
The segment made up of SOFCs is expected to have a value of nearly $302 million in 2012 and nearly<br />
$1.2 billion in 2017, a CAGR of 31%.<br />
As a segment, PEMFCs should total $175 million in 2012 and $339 million in 2017, a CAGR of 14.1%.<br />
Other FCs are expected to total $92 million in 2012 and $176 million in 2017, a CAGR of 13.9%.<br />
Fuel cell sizes range from tiny portable units that can be held in the hand to massive stacks the size of<br />
a building. Fuel cells can be combined into stacks in effectively unlimited sizes. This report considers “mediumsize”<br />
stationary fuel cells used in residential, commercial, and military settings. Like batteries, fuel cells produce<br />
electrical energy through an electrochemical process. Unlike batteries, fuel cells are “conversion”<br />
devices that change some kind of chemical fuel into electricity. Like combustion engines, fuel cells convert<br />
fuel into energy, but in this case, the energy is electricity rather than kinetic (movement) or heat.<br />
Report: $18 Billion<br />
Market for Electric<br />
Vehicle Inverters<br />
in 2023<br />
THE MARKET FOR ELECTRIC<br />
VEHICLE INVERTERS, including<br />
converters, for both<br />
hybrid and pure electric vehicles<br />
land, water and air, will grow<br />
to $18 billion in 2023 as forecasted<br />
in the new IDTechEx<br />
report “Inverters for Electric<br />
Vehicles 2013-2023”. For sheer<br />
volumes, inverters in light electric<br />
vehicles such as electric<br />
bicycles dominate now and will<br />
remain so by 2023, with these<br />
being largely in Asia, meeting<br />
everyday personal transportation<br />
needs in large industrial cities.<br />
However, by 2023, inverters<br />
and converters in passenger<br />
vehicles will dominant by market<br />
value as high volume production<br />
is established and cost of<br />
ownership and range anxiety<br />
are reduced. The user-demand<br />
for greater all electric range will<br />
push inverter and converter<br />
designers to optimize overall<br />
system efficiency. This, together<br />
with the need to reduce overall<br />
package size and system cost,<br />
will result in the adoption<br />
of new materials and control<br />
algorithms and undoubtedly<br />
require a move towards higher<br />
levels of system integration.<br />
Advances in inverter design<br />
for electric vehicles will assist<br />
in the realization of step<br />
changes in performance,<br />
size and reliability over the<br />
next decade, with materials<br />
such as Silicon Carbide and<br />
Gallium Nitride the most<br />
notable technology trends.<br />
4 <strong>Power</strong> <strong>Electronics</strong> Technology | January 2013 www.powerelectronics.com
For more than 50 years, Microwaves & RF has provided RF/<br />
microwave design engineers with the latest and most practical<br />
industry news, engineering guidance, and product reviews. It<br />
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manufacturing production—and in all locations around the world.<br />
It covers every market served by RF/microwave technologies,<br />
ranging from commercial wireless communications to automotive,<br />
defense, industrial, and medical applications. Microwaves & RF<br />
offers its engineering readers the latest technical information at all<br />
levels—from components and devices through systems and test.<br />
WHERE <strong>TECHNOLOGY</strong><br />
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INSIDE TRACK with<br />
TRACKING TRENDS<br />
COPPER MOUNTAIN’S<br />
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GROUP DESIGN DIRECTOR: ANTHONY VITOLO tony.vitolo@penton.com<br />
6 <strong>Power</strong> <strong>Electronics</strong> Technology | January 2013 www.powerelectronics.com<br />
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DESIGNfeature<br />
CHRISTIAN KUECK, Linear Technology Corp.<br />
Layout <strong>Power</strong><br />
Supply Boards<br />
to Minimize<br />
EMI: Part 1<br />
PC-board layout sets the<br />
functional, electromagnetic<br />
interference (EMI), and thermal<br />
behavior of a power<br />
supply. Good layout from first<br />
prototyping on actually saves<br />
significant resources in EMI<br />
filters, mechanical shielding,<br />
EMI test time and PC board<br />
runs. The design goal for this<br />
process is to minimize EMI by<br />
optimizing board layout.<br />
With non-isolated topologies, one of the most basic topologies<br />
is the buck regulator. EMI starts off from high di/dt<br />
loops. The supply wire as well as the load wire should not<br />
have high AC current content. So, we can focus our analysis<br />
from the input capacitor, C IN , which should source all<br />
relevant AC currents to the output capacitor, C OUT , where<br />
any AC currents end. To minimize EMI, we have to determine<br />
the “hot” loop in the circuit and reduce its impact.<br />
In the on cycle of a buck converter AC current follows through the red loop with<br />
S1 closed and S2 open (Fig. 1.). During the off cycle, with S1 open and S2 closed,<br />
AC current follows through the blue loop. Both currents have a trapezoid shape.<br />
Designers often have difficulty grasping that the loop producing the highest EMI<br />
is not the red or the blue loop. Only in the green loop flows a fully switched AC<br />
current, switched from zero to I PEAK and back to zero. We refer to the green loop<br />
as a hot loop, because it has the highest AC and EMI energy.<br />
To reduce EMI and improve functionality, you need to reduce the radiating effect<br />
of the green loop as much as possible. If we could reduce the PC-board area of the<br />
green loop to zero and buy an ideal input capacitor with zero impedance, the problem<br />
V IN<br />
+<br />
–<br />
C IN<br />
HOT LOOP<br />
8 <strong>Power</strong> <strong>Electronics</strong> Technology | January 2013 www.powerelectronics.com<br />
S1<br />
S2 C OUT<br />
AN139 F01<br />
Fig. 1. Non-isolated buck topology in which the loop producing the highest EMI is the green, or hot loop<br />
V OUT
would be solved. But in the real world,<br />
we must find the optimal compromise.<br />
In the schematic in Fig. 2, the<br />
hot loop of the LT8611 buck converter<br />
is not easy to spot for layout<br />
purposes. Fig. 3 shows an LT8611<br />
buck converter demo board layout.<br />
Both switches are internal, so we<br />
only have to be concerned with the<br />
connection of the input capacitor.<br />
As shown Fig. 3, the green line is the<br />
hot loop in the top layer. AC current<br />
flows through the input capacitor<br />
and the switches in the part.<br />
A copper short-circuit loop or<br />
plane under the hot loop improves<br />
the functional and EMI behavior of<br />
your circuit. Table 1 shows the result<br />
of an experiment with a 10 cm ×<br />
10 cm rectangular loop operating<br />
at 27MHz. The table indicates how<br />
much improvement a solid copper<br />
plane gives under the hot loop topside<br />
traces. The first line is no plane<br />
single layer. The inductance of a<br />
single-layer loop of 187 nH gets down<br />
to 13 nH in the case of only 0.13<br />
mm insulation between the plane<br />
and loop traces. A solid plane on the<br />
next layer in a multilayer board (four<br />
layers or more) will have over 3× less<br />
inductance than a normal 1.5-mm,<br />
two-layer board with a solid bottom<br />
plane, and over 14× less over a<br />
single-layer board. A solid plane with<br />
minimum distance to the hot loop<br />
is one of the most effective ways to<br />
reduce EMI.<br />
WHERE DOES THE CURRENT<br />
FLOW IN THE PLANE?<br />
The green top layer hot loop magnetic<br />
AC field produces eddy currents<br />
in the plane (Fig. 4). Those eddy currents<br />
produce a mirror AC magnetic<br />
field, which is opposite the hot loop<br />
field (red trace). Both magnetic fields<br />
will cancel out. This works better the<br />
closer the mirror current is to the hot<br />
loop. Current is a round trip in the<br />
top layer. The most likely current<br />
path in the shield is the same round<br />
trip direct under the top layer. Both<br />
TABLE 1: RESULTS OF A 10 cm × 10 cm<br />
RECTANGULAR LOOP OPERATING WITH A COPPER<br />
SHORT-CIRCUIT LOOP OR PLANE UNDER THE HOT LOOP.<br />
D (mm) F (MHz) C (pF) L (nH)<br />
V IN<br />
5.5 V<br />
to 42 V 4.7<br />
μF<br />
18.4 400 187<br />
21.2 400 141<br />
1 μF<br />
f SW = 700 kHz<br />
ON OFF<br />
www.powerelectronics.com January 2013 | <strong>Power</strong> <strong>Electronics</strong> Technology 9<br />
0.1 μF<br />
60.4 k<br />
V IN<br />
EN/UV<br />
SYNC<br />
LT8611<br />
IMON<br />
ICTRL<br />
INTV CC<br />
TR/SS<br />
RT<br />
PGND<br />
BST<br />
SW<br />
ISP<br />
ISN<br />
BIAS<br />
PG<br />
FB<br />
GND<br />
Single-Layer<br />
Open Loop<br />
Inner Copper<br />
Short-Circuit Loop<br />
0.1 μF<br />
4.7 μH<br />
10 pF<br />
1M<br />
243 k<br />
0.02 Ω<br />
1 μF<br />
FACTOR OVER<br />
0.12 mm<br />
14.4<br />
10.85<br />
1. 5 38.9 400 42 Solid Plate 3.23<br />
1. 5 34.7 400 53<br />
Rectangular Loop<br />
No Overlap<br />
4.08<br />
0. 5 52.1 400 23 Thin Rectangular 1.77<br />
0. 27 55 400 21 1.61<br />
0. 12 69 400 13 Paper<br />
Fig. 2 Schematic of the LT8611 buck converter.<br />
Fig. 3. Layout of the LT8611buck converter in which<br />
the green line is the hot loop in the top layer.<br />
AN139 F02<br />
V OUT<br />
5 V<br />
2.5 A<br />
47 μF<br />
Fig. 4. The green top layer loop produces eddy cur-<br />
rents within the red loop.
POWER SUPPLYemi<br />
currents are almost the same. Since the plane<br />
current needs to be as high as the top trace<br />
current, it will produce as much voltage across<br />
the plane as is necessary to sustain the current.<br />
To the outside it will show up as GND bounce.<br />
From an EMI perspective, small hot loops<br />
are best. The EMI from a power supply IC<br />
with integrated sync switches, optimized<br />
pinout and careful internal switch control<br />
will be less than a non-sync power supply<br />
IC with external Schottky diode. And, both<br />
will outperform a controller solution with<br />
external MOSFETs.<br />
VIN +<br />
_<br />
The boost circuit can be viewed in continuous mode as a<br />
buck circuit operating backwards. The hot loop is identified<br />
as the difference between the blue loop if S1 is closed and<br />
the red loop (Fig. 5) with S1 open and S2 closed.<br />
V IN<br />
+<br />
_<br />
C IN<br />
S2<br />
S1<br />
HOT LOOP<br />
C OUT<br />
AN139 F06<br />
V OUT<br />
Fig. 5. The hot loop is the difference between the blue loop and the red loop with<br />
S1 open and S2 closed.<br />
Fig. 6. The hot loop of the LT3956 LED driver boost controller is shown in green.<br />
HOT LOOP HOT LOOP<br />
Fig. 6 shows the green hot loop of an LT3956 LED<br />
driver boost controller. The second layer is a solid GND<br />
plane. The main EMI emitter is the magnetic antenna the<br />
hot loop creates. The area of the hot loop and its inductance<br />
are tightly related. If you are comfortable thinking<br />
in inductance, try to decrease it as much as you can. If<br />
you are more comfortable in antenna design, reduce the<br />
effective area of the magnetic antenna. For near field purposes,<br />
inductance and magnetic antenna effectiveness are<br />
essentially the same.<br />
The single inductor, four-switch buck-boost topology<br />
(Fig. 7) consists of a buck circuit followed by a boost circuit.<br />
The layout will often be complicated by a common<br />
GND current shunt that belongs to both hot loops. An<br />
LTC3780 demo board (Fig. 8) shows an elegant solution<br />
splitting the sense resistor in two parallel ones.<br />
A bit different drawing of a SEPIC circuit (Fig. 9) shows<br />
its hot loop. Instead of an active MOSFET for the top<br />
switch, a diode is often used. The LT3757 demo board (Fig.<br />
10 <strong>Power</strong> <strong>Electronics</strong> Technology | January 2013 www.powerelectronics.com<br />
V OUT<br />
AN139 F06<br />
Fig. 7. The four switch buck-boost converter consists of a buck circuit followed by a boost circuit.<br />
Fig. 8. LTC3780 demo board layout splits the sense resistor into two parallel ones.
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POWER SUPPLYemi<br />
V IN<br />
+<br />
_<br />
HOT LOOP<br />
Fig. 9. SEPIC circuit shows the hot loop in green.<br />
V OUT<br />
AN139 F10<br />
■ POWER SUPPLY EMI MEASUREMENTS<br />
MOST POWER SUPPLIES ARE RELATIVELY small compared to<br />
the wavelength of the relevant EMI frequencies they produce<br />
and are measured against. If prudently designed, in<br />
current power supply technology you will find most energy<br />
below 500MHz. EMI standards must be general and apply to<br />
equipment of variable size. Those can be in the order of the<br />
wavelength of interest. So they call for line conducted measurements<br />
up to 30 MHz and radiated measurements above<br />
30 MHz. However reliable radiated measurements require<br />
large anechoic chambers. Their hourly prices are high and<br />
availability is scarce. Free field is too noisy, requires a large<br />
and difficult setup and is weather dependent.<br />
For power supply optimization to work, a reasonable<br />
approach is to make line-conducted pre-compliance measurements<br />
up to the end of the spectrum required for radiated<br />
measurements. Since the power supply dimensions are still<br />
small against the wavelength of interest, we can assume that<br />
most energy will find its way through the V IN and V OUT wires,<br />
where we can measure them line conducted.<br />
The setup is quite simple. We need a LISN (line impedance<br />
stabilizer network) or AN (artificial network), an input<br />
supply, a load and a measurement receiver.<br />
The purpose of the LISN (AN) is to isolate the voltage<br />
source V1 from the power supply (or DUT device under test)<br />
V IN (V DUT + , VDUT ).<br />
This is an example of a non-symmetric LISN often used in<br />
automotive applications (Fig. 13). Such a simple circuit can<br />
be made with L1 as air coil, or an inductor with losses can be<br />
used. Some standards specify different core types in series<br />
and a special winding scheme. However, the main purpose is<br />
to create a wideband high impedance against 50 Ω for L1.<br />
Other than the wire length inside for C1, R1 and the<br />
V OUT_HF and L1 impedance, nothing limits the usable upper<br />
frequency range. So buy one or build your own. Resonances of<br />
L1 can be damped with a resistor over a part of L1 windings.<br />
Fig. 10. Good SEPIC layout in which the hot loop area is minimized and has a solid<br />
ground plane on the next layer.<br />
Any dedicated EMI receiver can be used, but a spectrum<br />
analyzer will usually do for pre-compliance work. Make<br />
sure that you use the AC-coupled input, since it provides<br />
a second barrier against blowing up your expensive mixer<br />
inside the analyzer.<br />
From the EMI lab experts, you can expect a lengthy discussion<br />
about the required detection method from the used EMI<br />
standard, including peak, quasi peak, average with relative<br />
accurate time constants required for them. You can shortcut<br />
this discussion when your power supply operates fixed frequency<br />
in the load area of interest. At fixed frequency, only<br />
harmonics with a distance of the switching frequency can<br />
be created, a frequency comb. If the switching frequency is<br />
above the required resolution bandwidth (mostly 9 kHz up to<br />
30 MHz and 120 kHz above 30 MHz), peak, quasi-peak and<br />
average methods will yield the same results, so you can use<br />
whatever your receiver provides. Some standards allow for the<br />
9 kHz to use a 10 kHz bandwidth, and for 120 kHz, using a<br />
100 kHz bandwidth. The error for a fixed frequency switching<br />
PSU, which operates well above 100 kHz, is not relevant for<br />
our pre-compliance task.<br />
If your system includes a processor it can produce currents<br />
with large fluctuations with frequency contents well within the<br />
above resolution bandwidth.<br />
Then, you need to refrain to the filter method your standard<br />
requires.<br />
If you see components that are a fraction of the switching<br />
frequency or cannot be divided by integers to the switching<br />
frequency, check the switch node with an oscilloscope.<br />
In the time domain, you will likely see pulse skipping or<br />
subharmonic oscillation. Check the source for this behavior<br />
before proceeding further. Do not forget to unhook your scope<br />
probe because you get different results with the additional<br />
introduced probe antenna if you do EMI measurements with<br />
a probe attached.<br />
12 <strong>Power</strong> <strong>Electronics</strong> Technology | January 2013 www.powerelectronics.com
power supplyemi<br />
–V OUT<br />
V IN<br />
10) shows a good SEPIC layout. The green hot loop area is<br />
minimized and has a solid GND plane on the next layer.<br />
INVERTING, FLYBACK TOPOLOGIES<br />
The inverting topology (Fig. 11) is very similar to SEPIC,<br />
only the load has moved through the top switch and top<br />
inductor. Layout is very similar, and demo boards can<br />
typically be modified from SEPIC to inverting provided<br />
the IC can also regulate on negative feedback voltage like<br />
LT3581, LT3757 etc.<br />
The flyback topology (Fig. 12) uses separate windings<br />
on a transformer and there is only magnetic coupling<br />
between the primary and secondary windings. The current<br />
in the primary winding goes to zero at a relative high di/<br />
dt; only the energy stored in the leakage inductance and<br />
capacitance between windings and on the switch node<br />
slows that down. The primary and other transformer<br />
windings can be seen as fully switched current. We get two<br />
1<br />
2<br />
+ _<br />
10 mH<br />
HOT LOOP<br />
AN139 F12<br />
Fig. 11. The inverting topology is similar to the SEPIC, except the load has moved<br />
through the top switch and top inductor.<br />
~<br />
+<br />
~ –<br />
High HF Impedance<br />
main hot loops as in the buck-boost case (Fig.7). To reduce<br />
EMI, in addition to close V IN decoupling for differential<br />
mode EMI, common mode chokes are used for the likely<br />
dominant common mode EMI in this topology.<br />
For more information on reducing EMI, see the sidebar<br />
“<strong>Power</strong> Supply EMI Measurements.”<br />
RefeRences<br />
[1] http://www.conformity.com/past/0102reflections.html<br />
[2] http://www.ece.msstate.edu/~donohoe/ece4990notes5.pdf<br />
[3] http://de.wikipedia.org/wiki/Skin-Effekt 1.3.2011<br />
[4] Rudnev, Dr. Valery I.; Heat Treating Progress; Oct. 2008<br />
[5] Archambeault,Bruce R.; PCB Design for Real-World EMI Control; 2002<br />
[6] Williams, Tim; EMC For Product Designers; Second Edition; 1996<br />
[7] Johnson Howard, Graham, Martin; High Speed Digital Design A Handbook<br />
Of Black Magic; 1993<br />
[8] Zhang, Henry J.; PCB Layout Considerations For Non-Isolated Switching<br />
<strong>Power</strong> Supplies; AN136; www.linear.com<br />
[9] Ott, Henry W.; Electromagnetic Compatibility Engineering; Wiley; 2009<br />
LT, LTC, LTM, Linear Technology, the Linear logo and LTspice are registered<br />
trademarks of Linear Technology Corporation. All other trademarks are the<br />
property of their respective owners.<br />
HOT LOOP<br />
HOT LOOP<br />
AN139 F13<br />
14 <strong>Power</strong> <strong>Electronics</strong> Technology | January 2013 www.powerelectronics.com<br />
+ –<br />
V1<br />
12 V<br />
L1<br />
5 μH<br />
C2<br />
100 μF<br />
LISN<br />
C1<br />
100 nF<br />
R1<br />
1k<br />
V OUT_HF<br />
R2<br />
50 Ω<br />
V DUT+<br />
V DUT-<br />
AN139 F41<br />
Fig. 13. Example of a non-symmetric LISN (line impedance stabilizer network)<br />
often used in automotive applications.<br />
Fig. 12. Flyback circuit uses separate transformer windings in which there is only magnetic coupling between primary and secondary.<br />
3<br />
4
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I SD —Source to Drain Current (A)<br />
designfeature<br />
Johan Strydom, Ph.d., V.P., Applications, Efficient <strong>Power</strong> Conversion Corporation<br />
david reuSch, Ph.d., Director, Applications, Efficient <strong>Power</strong> Conversion Corporation<br />
eGaN ® FET- Silicon <strong>Power</strong> Shoot Out<br />
Volume 12: Optimizing Dead Time<br />
Significant efforts have been<br />
made to show the performance<br />
improvements achievable<br />
with eGaN ® fEts over<br />
silicon mOSfEts in both hard<br />
and soft switching applications.<br />
this volume of the eGaN<br />
fEt-Silicon power shoot-out<br />
series continues to examine<br />
the optimization trend [1] and<br />
look at the impact of deadtime<br />
on system efficiency for<br />
eGaN fEts and mOSfEts.<br />
100<br />
90<br />
MOSFET<br />
80<br />
25˚C<br />
70<br />
125˚C<br />
60<br />
+Q RR<br />
50<br />
40<br />
30<br />
20<br />
10<br />
0<br />
eGaN FET<br />
25˚C<br />
125˚C<br />
+Zero Q<br />
RR<br />
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5<br />
VSD —Source to Drain Voltage (V)<br />
fig. 1. Reverse transfer characteristics of equivalent<br />
100 v mOSfEt and eGaN fEt at 25°c and 125°c.<br />
Initial shoot-out articles [2, 3] showed that eGaN FETs behave similarly to silicon<br />
devices and can be evaluated using the same performance metrics. Although<br />
eGaN FETs perform significantly better by most metrics, the eGaN FET ‘bodydiode’<br />
forward voltage is higher than its MOSFET counterpart and can be a<br />
significant loss component during dead-time. Body diode forward conduction<br />
losses alone do not make up all dead-time dependent losses. Diode reverserecovery<br />
and output capacitance losses are also important. We will discuss<br />
dead-time management and the need to minimize all dead-time losses.<br />
To start, consider the reverse transfer characteristics for both MOSFETs and<br />
eGaN FETs, shown in Fig. 1. This figure shows a 1.5 V increase in forward voltage<br />
drop of the eGaN FET ‘body diode’ compared to a Si MOSFET at 25°C, as temperature<br />
increases the voltage difference increases to almost 2 V. What isn’t shown<br />
is that since the eGaN FET ‘diode’ is just the channel conducting in reverse and a<br />
majority carrier operation; this results in no diode reverse-recovery charge in eGaN<br />
FETs. Body diode forward conduction and reverse recovery losses are not the only<br />
dead-time related losses; there are output capacitance losses and additional switching<br />
losses when the self-commutation time is longer than the allotted dead-time.<br />
EffEctivE dEad-timE<br />
For this analysis presented, effective dead-time will be used. The effective deadtime<br />
is defined from when one device reaches turn-off threshold (V TH ) voltage<br />
on the gate to when the other device, which is turning on, reaches its threshold<br />
voltage. For a constant controller dead-time, the effective dead-time depends on<br />
variations in device threshold voltage, gate resistance, and gate capacitance. The<br />
resultant effective dead-time also depends on device operating voltage and the<br />
pulse-width variation in the gate drive circuit.<br />
There are only a limited number of ways to have the body diode conduct<br />
during dead-time period. To determine the effect of gate timing on body diode<br />
losses, all of these device states will be considered. In simple terms, there is the<br />
possibility for body diode conduction at both turn-on and turn-off of a device.<br />
To have diode conduction at device turn-off, a negative current must be flowing<br />
from source to drain (positive current defined as flowing drain to source), such<br />
as the turn-off of a synchronous rectifier in a buck converter. For negative currents<br />
(diode conduction at device turn-off), the next device turn-on will always<br />
be hard switching and require reverse recovery of the conducting diode. There is<br />
some evidence [4, 5] to suggest that the reverse recovery losses in MOSFETs can<br />
be reduced by limiting the commutation time of the body diode, but much of<br />
this depends on the MOSFET diode forward recovery, which is not available. In<br />
most cases, the current commutates fully to the body diode, resulting in eventual<br />
diode reverse recovery and more dead-time.<br />
For diode conduction at turn-on, the drain voltage across the device turning<br />
on must be externally commutated by a positive current flowing into of the<br />
16 <strong>Power</strong> <strong>Electronics</strong> Technology | January 2013 www.powerelectronics.com
drain terminal, such as the dead-time interval before the<br />
turn-on of a synchronous rectifier in a buck converter.<br />
For such positive currents, the analysis is more complex<br />
as drain voltage across the turn-off device starts increasing<br />
and is load current dependent. If there is enough<br />
energy in the inductor to commutate the voltage completely,<br />
lossless zero voltage switching (ZVS) turn-on<br />
can be achieved, but increasing dead-time further will<br />
only incur additional diode conduc-<br />
tion losses. Reducing dead-time below<br />
that required for ZVS will cause hardswitching<br />
at reduced switching voltage<br />
and will also increase losses. Thus,<br />
for positive currents, there are load<br />
current dependent optimum effective<br />
dead-time values. Fig. 2 shows the full<br />
range of drain to source voltage waveforms<br />
for both negative and positive<br />
currents for a given dead-time. The<br />
waveforms are color coded to represent<br />
relative dead-time dependent<br />
commutation loss, from maximum<br />
loss (Dark Red), down to pure lossless<br />
commutation (Blue).<br />
For this analysis, the switching<br />
loss at both turn-on and turn-off are<br />
neglected, as these are not dead-time<br />
dependent. But, as discussed above, it<br />
is possible to incur additional synchronous<br />
rectifier hard-switching turn-on<br />
losses for positive currents where<br />
dead-time is insufficient to allow commutation.<br />
Additionally, body diode<br />
conduction, output capacitance losses<br />
(E OSS ), and diode reverse recovery<br />
losses (E QRR ) are considered. The special<br />
case of zero-current turn-off is<br />
also shown. In this case, the zerocurrent<br />
switching (ZCS) turn-on will<br />
incur only E OSS losses.<br />
To optimize efficiency and minimize<br />
dead-time commutation losses,<br />
different load current ranges at both<br />
turn-on and turn-off dead-time intervals<br />
are important. The range of the<br />
dead-time commutation waveforms<br />
shown in Fig. 2 is meant to be exhaustive<br />
and will be much larger than<br />
needed for most specific applications<br />
and specific dead-time intervals. Since<br />
we need to compare eGaN FETs and<br />
silicon MOSFETs over a wide range of<br />
voltages and applications, the whole<br />
Device Turn-off<br />
Bus Voltage<br />
High Loss<br />
No Loss<br />
load current range of Fig. 2 will be considered. It will<br />
then be possible to select a subset of these for a specific<br />
application dead-time interval and determine the<br />
required optimization conditions for it. To represent<br />
the wide range of possible dead-time losses and quickly<br />
compare FET technologies, Fig. 3 shows a graphical representation<br />
of the energy loss as function for the whole<br />
range of currents. The specific dead-time value used in<br />
Negative current<br />
causing diode conduction<br />
Increasing Current<br />
Zero Current<br />
Positive current causes<br />
self commutation<br />
Effective Dead-time<br />
Device Turn-on<br />
Turn-off device has<br />
diode reverse recovery<br />
Turn-on device is hard-switching<br />
Partial ZVS turn-on,<br />
No reverse recovery, but<br />
Dead-time dependent<br />
hard-switching losses<br />
Optimal dead-time<br />
Lossless commutation<br />
www.powerelectronics.com January 2013 | <strong>Power</strong> <strong>Electronics</strong> Technology 17<br />
GND<br />
ZVS turn-on with diode conduction<br />
time increasing with current<br />
Fig. 2. Idealized drain-source voltage commutation waveforms for varying load current at a given dead-time<br />
(Dark Red to Blue coloring represents high loss to no loss)<br />
Energy loss due to dead-time (µJ)<br />
Shoot-through<br />
Additional<br />
switching losses<br />
Increasing<br />
current<br />
Dead-time used in<br />
Figure 2<br />
Partial ZVS / Reduced<br />
Voltage Switching<br />
Effective Dead-time (ns)<br />
Zero Current<br />
ZVS<br />
Increasing diode<br />
conduction losses<br />
Hard Switching<br />
E QRR<br />
E OSS<br />
Increasing diode<br />
conduction losses<br />
Lossless<br />
Fig. 3. Idealized dead-time related loss per cycle for different load currents versus dead-time (Red to blue<br />
coloring represents high loss to no loss).
eGaNfets<br />
Fig. 2 becomes a single point along the x-axis with each<br />
commutation waveform resulting in a separate energy<br />
loss number (colored circles).<br />
For this analysis, two devices in a half-bridge (totempole)<br />
configuration are assumed and reduced voltage<br />
hard-switching turn-on, output capacitance, body diode<br />
and reverse recovery losses are calculated using equations<br />
from Table 1 of [1] and calculating the parameters<br />
from the respective device datasheets. These equations<br />
Energy loss per event (µJ)<br />
Energy loss per event (uJ)<br />
15<br />
14<br />
13<br />
12<br />
11<br />
10<br />
9<br />
8<br />
7<br />
6<br />
5<br />
4<br />
3<br />
2<br />
1<br />
20 A<br />
0<br />
0<br />
1.0<br />
0.9<br />
0.8<br />
0.7<br />
0.6<br />
0.5<br />
0.4<br />
0.3<br />
0.2<br />
100 V EPC2001 eGaN FET 80 V BSC057N08NS3 MOSFET<br />
4 A<br />
–20 A<br />
0 A<br />
Energy loss per event (µJ)<br />
15<br />
14<br />
13<br />
12<br />
11<br />
10<br />
9<br />
8<br />
7<br />
6<br />
5<br />
4<br />
3<br />
4 A<br />
are repeated in Table 1 and rewritten to accommodate<br />
reduced voltage switching and energy loss per dead-time<br />
interval calculation.<br />
eGaN FET - MOSFET COMPARISON<br />
The dead-time losses in a 60 V bus half-bridge application<br />
using 100 V eGaN FETs [6] and similar R DS(ON)<br />
state of the art 80 V MOSFETs [7] are shown in Fig.<br />
4. The lines are drawn in 4 A load steps from –20 A<br />
–20 A<br />
to +20 A. The comparison clearly<br />
shows the following differences:<br />
1. Self commutation times for eGaN<br />
FETs are about half as long as those of<br />
the MOSFETs due to lower output<br />
capacitance.<br />
2. Stored energy losses and diode reverse<br />
recovery losses in eGaN FETs are 36%<br />
that of MOSFETs due to lack of reverse<br />
recovery and lower output capacitance.<br />
3. Body diode conduction loss increases<br />
with time in eGaN FETs is about 2.5<br />
times faster than MOSFETs due to<br />
the higher diode conduction voltage.<br />
4. Optimum dead-time range depends<br />
on load current, but with the eGaN<br />
FETs, this range is about 50% that<br />
of the MOSFET.<br />
For practical designs where a single<br />
dead-time is used for all load current<br />
conditions, the values might be 20 ns<br />
±7 ns and 44 ns ±16 ns respectively<br />
and would yield similar sub 1 mJ<br />
dead-time loss results (areas highlighted<br />
in orange in Fig. 4). Lower<br />
dead-time losses are possible, but<br />
would require tighter tolerances and/<br />
or dynamic dead-time optimization.<br />
In lower voltage applications,<br />
the effect of the body diode is more<br />
pronounced relative to other losses.<br />
Consider such a 12 V buck application<br />
using 40 V eGaN FETs [8] and similar<br />
R DS(ON) state of the art 30 V MOSFETs<br />
[9] with dead-time losses (Fig. 5.) The<br />
lines are again drawn in 4 A load steps<br />
from -20 A to +20 A. The comparison<br />
is similar to the 60 V case except for<br />
comparison numbers 2 and 4, which<br />
have the following differences:<br />
2. In eGaN FETs, hard commutation<br />
stored energy losses and diode reverse<br />
recovery losses have increased to 45%<br />
relative to that of MOSFETs.<br />
18 <strong>Power</strong> <strong>Electronics</strong> Technology | January 2013 www.powerelectronics.com<br />
–4 A<br />
10 20 30 40<br />
2<br />
1<br />
20 A<br />
0<br />
0 10 20 30 40 50 60 70 80 90 100<br />
Effective Dead-time (ns) Effective Dead-time (ns)<br />
Fig. 4. Calculated dead-time losses per cycle versus dead-time for both eGaN FET and MOSFET in a 60 V<br />
application (-20 A to +20 A in 4 A steps).<br />
40 V EPC2015 eGaN FET 30 V BSC034N03LS MOSFET<br />
1.0<br />
–20 A<br />
0 A<br />
–20 A<br />
Energy loss per event (µJ)<br />
0.1<br />
0.1<br />
20 A<br />
4 A<br />
20 A<br />
0.0<br />
0 2 4 6 8 10<br />
0.0<br />
0 4 8 12 16 20 24<br />
Effective Dead-time (ns) Effective Dead-time (ns)<br />
Fig. 5. Calculated dead-time losses per cycle versus dead-time for both eGaN FET and MOSFET in a 12 V<br />
application (-20 A to +20 A in 4 A steps).<br />
0.9<br />
0.8<br />
0.7<br />
0.6<br />
0.5<br />
0.4<br />
0.3<br />
0.2<br />
4 A<br />
0 A<br />
0 A<br />
–4 A
4. Optimum dead-time range is still about 50% that of<br />
MOSFET, but both are much smaller. (The 4 A to 20 A<br />
eGaN FET dynamic optimum range is just 3 to 6 ns vs. 7<br />
to 13 ns for MOSFETs). For a constant dead-time design,<br />
both dead-time ranges (Fig. 5) are less than 6 ns wide and<br />
may be difficult to generate this required accuracy. Lower<br />
TABLE 1: EQUATIONS USEd TO cALcULATE<br />
EffEcTIvE dEAd-TImE ENErgy LOSS<br />
pEr dEAd-TImE INTErvAL<br />
Device Turn-On Loss<br />
Diode Reverse<br />
Recovery Loss<br />
Output Capacitance<br />
Charge Loss<br />
Body Diode<br />
Conduction Loss<br />
dead-time losses are plausible, but would require even<br />
tighter tolerances and/or dynamic dead-time optimization.<br />
eGaN FET<br />
Schottky<br />
diode<br />
Place diode and eGaN FET side-by-side to minimize inductance<br />
Low<br />
package<br />
impedance<br />
Fig. 6. Suggested layout for adding an external Schottky with eGaN FETs.<br />
www.powerelectronics.com January 2013 | <strong>Power</strong> <strong>Electronics</strong> Technology 19
eGaNfets<br />
Given the current lack of capability for<br />
0.9<br />
such tight tolerances for most MOSFET<br />
driver and MOSFET combinations, a com- 0.8<br />
mon alternative solution to such a small<br />
0.7<br />
dead-time range is to minimize dead-time<br />
losses over a more realistic range by add- 0.6<br />
ing a parallel Schottky diode. In silicon,<br />
0.5<br />
this is only effective when the Schottky<br />
diode is monolithically integrated into the 0.4<br />
MOSFET, as the small voltage drop differ-<br />
0.3<br />
ence between the body diode and Schottky<br />
diode together with the large loop induc- 0.2<br />
tance between them would mean a too<br />
0.1<br />
long commutation time to be practical<br />
20 A<br />
[10] . Furthermore, partial commutation 0.0<br />
to the Schottky diode would mean that<br />
the MOSFET body diode would still have<br />
to recover at turn-off with the additional<br />
associated recovery losses. Alternatively,<br />
lengthening the diode conduction time to<br />
allow complete commutation will incur additional diode<br />
conduction losses instead.<br />
For eGaN FETs, the case is very different. First, there is<br />
no body diode reverse recovery, so even with partial current<br />
commutation from the body diode to the Schottky<br />
diode it would still reduce overall dead-time losses.<br />
Second, the much higher body diode forward drop is<br />
actually beneficial for the addition of a Schottky diode here<br />
Efficiency (%)<br />
90<br />
89<br />
88<br />
87<br />
86<br />
85<br />
84<br />
83<br />
82<br />
81<br />
80<br />
4 6 8 10<br />
Energy loss per event (µJ)<br />
1.0<br />
70% loss reduction<br />
with external Schottky diode<br />
No improvement for<br />
external Schottky diode<br />
Total dead-time cycle is twice per interval<br />
eGaN FET, 5 ns dead-time<br />
eGaN FET + Schottky, 5 ns dead-time<br />
eGaN FET, 10 ns dead-time<br />
eGaN FET + Schottky, 10 ns dead-time<br />
40 V EPC2015 eGaN FET 40 V EPC2015 eGaN FET + 3 A Schottky<br />
1.0<br />
as it increases the current commutation speed by generating<br />
a larger voltage differential between the two diodes [11] .<br />
Third, the low parasitic inductance of the eGaN<br />
FET’s land grid array (LGA) package makes the addition<br />
of an external Schottky diode possible by reducing<br />
the commutation loop inductance. Care should be<br />
taken to minimize the Schottky diode package inductance<br />
and pcb loop also to avoid negating this advantage.<br />
This is best done by placing<br />
the Schottky diode next to the<br />
eGaN FET on the same side of the<br />
board and choosing a low inductance<br />
package Schottky [12, 13] .<br />
The improved thermal package<br />
parts with exposed tab are good<br />
as they remove one or both wirebond<br />
connections. A suggested<br />
layout is shown in Fig. 6.<br />
Following the same loss calculation,<br />
the effect of adding a 3 A<br />
Schottky diode to the eGaN FET in<br />
a 12 V application can be seen in<br />
Fig. 7 (right) compared to the standard<br />
eGaN FET with no Schottky<br />
diode (left). We can draw the following<br />
conclusions:<br />
1. Adding a Schottky diode increases<br />
output capacitance losses and<br />
lengthens self-commutation time.<br />
Choosing the right size Schottky<br />
diode is important to balance the<br />
capacitive loss increase with reduced<br />
diode conduction losses.<br />
20 <strong>Power</strong> <strong>Electronics</strong> Technology | January 2013 www.powerelectronics.com<br />
0 A<br />
–20 A<br />
Energy loss per event (µJ)<br />
4 A<br />
0.1<br />
20 A<br />
0.0<br />
0 2 4 6 8 10 0 4 8 12 16 20 24<br />
Effective Dead-time (ns) Effective Dead-time (ns)<br />
~1% efficiency drop<br />
per 10 ns total<br />
50%<br />
loss<br />
reduction<br />
~1% efficiency drop<br />
per 20 ns total<br />
12 14 16 18 20 22<br />
Output Current (IOUT )<br />
eGaN FET, Optimum dead-time<br />
MOSFET Optimum dead-time<br />
MOSFET, 10 ns dead-time<br />
MOSFET + Schottky, 10 ns dead-time<br />
0.9<br />
0.8<br />
0.7<br />
0.6<br />
0.5<br />
0.4<br />
0.3<br />
0.2<br />
Additional<br />
diode<br />
Small increase capacitance<br />
in<br />
losses<br />
self<br />
commutation –20 A<br />
time<br />
Fig. 7. Calculated dead-time losses per cycle versus dead-time for eGaN FET without and with external<br />
Schottky diode in a 12 V application (-20 A to +20 A in 4 A steps).<br />
Fig. 8. Experimental efficiency shown for 40 V eGaN FET and MOSFET buck converters operating at 1 MHz, 12 V IN<br />
and 1.2 V OUT with different effective dead-time values (same on both edges) and with/without external Schottky diode.<br />
4 A<br />
0 A
2. The diode conduction losses are decreased to about<br />
40% for a 3 A Schottky diode and are in direct relation<br />
to the decrease in the forward diode conduction drop.<br />
Optimal scaling of the Schottky diode can improve this<br />
for a selected load range.<br />
3. The practical dead-time range (for
designfeature<br />
Andy MoRRish, Chief Technology Officer of Semiconductor Products, Bourns, Inc.<br />
Limitations of Traditional<br />
Circuit Protection for High<br />
Energy Surge Threats<br />
There are limitations to older<br />
circuit protection solutions<br />
that use Transient Voltage<br />
Suppressor (TVS) diodes.<br />
Responding to this situation,<br />
completely new transient<br />
current suppressors utilize<br />
high-speed, bidirectional, low<br />
resistance, compact current<br />
limiting devices to protect<br />
circuits from overcurrent<br />
surges.<br />
In the quest for higher speed and lower costs, today’s modern electronics use<br />
increasingly dense integrated circuit technologies, whose sensitivity to surges<br />
creates difficult challenges for designers. Interfaces of equipment can be exposed<br />
to a wide range of dangerous surges, including Electrostatic Discharge (ESD)<br />
and lightning. Even with ESD immune optical fibers transmitting data long<br />
distances, connection from the optical-electrical interface equipment to offices<br />
and residential buildings is still mostly through external conventional electrical<br />
cabling, exposing this equipment to high energy electrical surges. As technology<br />
advances, older circuit protection solutions for the prevention of high-energy surge<br />
damage become less effective.<br />
Unlike conventional TVS diode protection, a new solution improves the robustness<br />
without the expense of adding capacitive devices that can rob bandwidth and<br />
reduce data rate performance. Lower voltage drivers can safely use very low capacitance,<br />
higher voltage clamping methods while still achieving protection that is far<br />
superior to even multiple stage TVS diode circuits. There are additional advantages<br />
of this new two-stage protection scheme.<br />
TVS DioDe BaSicS<br />
To understand the benefits<br />
of the new two-stage<br />
protection, we will first<br />
review TVS diodes that<br />
absorb ESD energy at the<br />
interface of a design. Fig.<br />
1 shows the basic operation<br />
of a TVS diode.<br />
Typically, the TVS diode<br />
appears as high impedance<br />
in the normal range<br />
of the signal working<br />
voltage that passes over<br />
the line. When a surge<br />
at the interface exceeds<br />
a preset limit, the TVS<br />
diode becomes conductive,<br />
quickly limiting the<br />
voltage from rising above<br />
this safe level. The ideal<br />
TVS diode in essence,<br />
has a “brick wall” clamping<br />
electrical characteristic<br />
that causes no inter-<br />
Protected<br />
Device<br />
The voltage limiting device<br />
is in a high impedance state<br />
when the signal is below the<br />
clamp voltage<br />
Protected<br />
Device<br />
When the surge voltage exceeds<br />
a preset limit, the ideal clamp<br />
conducts, absorbing the<br />
surge energy<br />
Normal Operation<br />
The signal flows freely in and<br />
out of the protected device<br />
22 <strong>Power</strong> <strong>Electronics</strong> Technology | January 2013 www.powerelectronics.com<br />
+<br />
–<br />
Surge Event With Ideal Clamp<br />
+<br />
–<br />
Surge<br />
Absorbed<br />
Energy<br />
Signal<br />
Fig. 1. Basic Operation of an Ideal Voltage Limiting Device<br />
Surge
ference to the normal signal, yet prevents the voltage at<br />
the interface from reaching an unsafe level.<br />
A TVS diode supports current flow in the form of<br />
avalanche, zener or punch-through breakdown, depending<br />
upon the construction of the device. This differs from<br />
the abruptly vertical characteristic of the ideal clamping<br />
device when we compare it to a typical semiconductor<br />
TVS diode. Although the real TVS diode seems highly<br />
resistant as the voltage increases, a finite “leakage” current<br />
begins to flow near the breakdown voltage of the junction.<br />
The larger the junction, the more leakage can occur which<br />
becomes troublesome because the current may negatively<br />
impact the operation of the circuit, particularly at higher<br />
temperatures.<br />
The TVS diode’s actual clamping characteristic is much<br />
softer than the abrupt vertical characteristic of the ideal<br />
clamp. The current increases gradually as clamping voltage<br />
is reached, avoiding the abrupt right angled characteristic.<br />
To ensure that the onset of clamping does not interfere<br />
with the signal, the clamping voltage must make allowances<br />
for this soft transition into clamping behavior, and<br />
the onset of clamping must be set higher than the ideal<br />
characteristic.<br />
As the current level continues to rise, a significant internal<br />
resistance of the TVS diode causes a distinct gradient<br />
in the voltage increase. As ESD devices may conduct tens<br />
or even hundreds of amps for short durations, the actual<br />
peak voltage that may be seen across the device, and therefore<br />
across the line, will be significantly higher than the<br />
onset of breakdown. The internal resistance is inversely<br />
proportional to the junction area. Therefore, achieving<br />
acceptably low clamping voltage at high levels of current<br />
may require a very large junction, which greatly impacts<br />
capacitance, cost and package size.<br />
Ultimately, simply connecting a TVS diode between<br />
an interface and ground is ineffective in protecting the<br />
device driving that interface. The device will experience<br />
the peak voltage developed across the TVS diode, and the<br />
voltage may reach 20 V during a discharge of 11 A. This<br />
is considerably beyond the capability of many low voltage<br />
technologies. Instead of effectively shielding the interface<br />
device from the surge, the TVS diode simply diverts a portion<br />
of the energy away. This exposes the device to high<br />
voltages and currents, which are often termed “let-through<br />
energy.” A potentially high level of let-through energy can<br />
be a major problem under surge conditions when using<br />
conventional TVS diodes for protecting sensitive electronics<br />
in harsh environments.<br />
TransienT CurrenT suppressor<br />
The growth in high-speed, low voltage applications that<br />
must withstand severe levels of lightning surge and ESD<br />
invites an alternative approach to the TVS diode and its<br />
Current Limit is Active<br />
inherent problems in achieving ideal characteristics. The<br />
basic limitations of the TVS diode stem from it being<br />
a single-stage protection device. Even the best voltage<br />
limiting device does not prevent current flow into the protected<br />
device, and it often cannot withstand the levels of<br />
current flow during the time when the clamping voltage is<br />
at its peak. The Transient Current Suppressor (TCS ) is a<br />
new device that significantly improves the level of protection<br />
when used in series with the protected signal line in<br />
a two-stage configuration together with a voltage limiting<br />
device. Fig. 2 shows the actual detailed characteristics of<br />
a TCS.<br />
Under normal operation, and when normal signal current<br />
is low, the TCS behaves like a low value resistor.<br />
Under surge conditions, when the current is driven above<br />
a certain limit, the TCS transitions very quickly into a current<br />
limiting state. Fig. 3 shows the TCS configuration and<br />
circuit symbol.<br />
The TCS adds a current limiting stage in series with the<br />
protected device to complement the characteristics of the<br />
voltage limiting device, thereby drastically reducing stress.<br />
The voltage at the interface increases when a surge occurs,<br />
causing current to flow through the TCS. As the current<br />
limit is reached, the TCS prevents further increase in current<br />
within its rated limits by allowing the voltage across<br />
itself to increase. This effectively presents a very high resistance.<br />
Current is thus limited to a constant level, voltage at<br />
the protected device no longer rises, and it is kept at a safe<br />
level. On the other side of the TCS, the voltage continues<br />
to rise until it reaches the activation voltage of the voltage<br />
clamping device.<br />
When used with a TCS, the first stage clamp voltage<br />
level no longer needs to be critically chosen to match<br />
the protected device, and its clamping characteristic may<br />
be much softer (resistive) than a single-stage TVS diode<br />
www.powerelectronics.com January 2013 | <strong>Power</strong> <strong>Electronics</strong> Technology 23<br />
Normalized Current<br />
1.2<br />
1.0<br />
0.8<br />
0.6<br />
0.4<br />
0.2<br />
0<br />
–0.2<br />
–0.4<br />
–0.6<br />
–0.8<br />
–1.0<br />
–1.2<br />
-40 -30 -20 -10 0<br />
Voltage (V)<br />
10 20 30 40<br />
Fig. 2. I-V Curve of a TCS.<br />
Maximum<br />
Voltage<br />
Linear Resistance<br />
(Slope = 1/Series<br />
Resistance)
CIRCUITprotection<br />
Protected<br />
Device<br />
Very Low<br />
Let-Through Energy<br />
Very fast TCS device reaction<br />
time (
100 pF. However, for direct comparison purposes, this<br />
simplified test circuit will demonstrate the effectiveness<br />
of the TCS protection system.<br />
When lightning surge transient voltages occur on the<br />
line, DSL circuits are often exposed to high levels of stress.<br />
C1 and C2 block DC bias voltages that may be present on<br />
POTS (Plain Old Telephone System) lines. Two capacitors<br />
were used in this test circuit in order to withstand<br />
the maximum voltage seen during surge. Often, a single<br />
higher voltage capacitor is used in the center tap instead;<br />
+<br />
–<br />
+<br />
–<br />
+<br />
–<br />
+<br />
–<br />
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C2<br />
56 nF<br />
Fig. 5. Equivalent Effect of GDT Firing, Causing Line Capacitor Discharge<br />
this does not affect the protection performance of the<br />
circuit. The surge causes the line side capacitors to charge,<br />
following the surge voltage as it rises to the point that the<br />
Gas Discharge Tube (GDT) fires. When this occurs, the<br />
GDT appears as a switch that has been suddenly closed,<br />
and the charged capacitors are switched instantly and<br />
directly across the line side winding of the transformer.<br />
The capacitor voltage, which is charged by the surge up<br />
to 500-1000 V, is then coupled across to the driver side<br />
winding. Very high discharge currents flow through the<br />
line side winding as the capacitors rapidly<br />
discharge through the GDT. As shown<br />
in Fig. 5, this induces current flow in the<br />
~ 750 V<br />
driver side, equal to that in the line side<br />
GDT<br />
multiplied by the turns ratio of the transformer.<br />
Surge Voltage VDSL transformers turns ratio usually<br />
ranges from 1:1 up to 1:4.5, depending<br />
upon the driver type. In the test circuit,<br />
a 1:1.4 ratio was used, which is a typical<br />
value for VDSL circuits. In the VDSL circuit,<br />
the driver is typically configured for<br />
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www.powerelectronics.com January 2013 | <strong>Power</strong> <strong>Electronics</strong> Technology 25
CIRCUITprotection<br />
active termination such that its output acts as virtual line<br />
termination. A combination of current and voltage feedback<br />
is used, so that the driver output impedance matches<br />
a significant portion of the reflected line impedance,<br />
as transformed through the driver transformer. With a<br />
ratio of 1:1.1, the 100 Ω line impedance transforms to<br />
the driver side by 1/n 2 where n is the turns ratio. In this<br />
case, the total equivalent resistance in the driver circuit<br />
including the R1 and R2 must equal 100/1.21 = 82.6 Ω.<br />
+<br />
–<br />
+<br />
–<br />
+<br />
–<br />
TCS-DL004-750-WH<br />
+<br />
–<br />
In addition, at 2.3 Ω, the nominal resistance of even the<br />
higher resistance TCS is very small in comparison to the<br />
driver side impedance, and it has negligible effect on the<br />
VDSL signal.<br />
R1 and R2 contribute to the protection by limiting<br />
some current between the voltage developed across the<br />
TVS diode and the output of the driver. However, their<br />
values must be kept relatively low compared to the line<br />
termination resistance, so that the amount of signal voltage<br />
dropped across them during normal operation is limited.<br />
Values typically range from 1 to 5 Ω. The lower<br />
value was used in this test. To demonstrate the TCS effectiveness,<br />
the 1 Ω resistors were replaced by a dual TCS<br />
with a nominal resistance of 1 Ω and a nominal current<br />
limit of 1.125 A, as shown in Fig. 6. The TVS diode was<br />
replaced by a simple diode clamp using generic diodes<br />
clamping to a generic 12 V zener (e.g. BZT52C12). This<br />
provided the necessary first stage of voltage clamping.<br />
This configuration forms an extremely low cost and very<br />
low capacitance clamp. Bias resistors of 10 kΩ between<br />
the zener and the supply rails can be used to minimize<br />
diode capacitance effects.<br />
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26 <strong>Power</strong> <strong>Electronics</strong> Technology | January 2013 www.powerelectronics.com<br />
VDSS<br />
Max<br />
(V)<br />
ID(cont)<br />
TC=25°C<br />
(A)<br />
RDS(on)<br />
max TJ=25°C<br />
(Ω)<br />
Ciss<br />
Typ<br />
(pF)<br />
Qg<br />
Typ<br />
(nC)<br />
trr<br />
Max<br />
(ns)<br />
PD<br />
(W)<br />
RthJC<br />
Max<br />
(ºC/W)<br />
MMIX1F44N100Q3 1000 30 0.245 13600 264 300 694 0.18<br />
Package<br />
Style<br />
SMPD
designfeature<br />
Shangyang Xiao, Applications Manager, Fairchild Semiconductor<br />
Ripple Generating Circuit for Constant-<br />
On-Time Controlled Buck Converters<br />
A ripple-generating circuit<br />
is usually needed to ensure<br />
stability of constant-on-time<br />
(COT) controlled buck converters.<br />
Different values of the<br />
ripple generating circuit can<br />
have direct impacts on output<br />
stability, and output regulation.<br />
However, a systematic<br />
approach optimizes the ripple<br />
generating circuit to meet<br />
stability criteria and maintain<br />
accurate DC regulation.<br />
Min Off<br />
Time<br />
– +<br />
On Time<br />
One Shot<br />
OR<br />
FB Vref<br />
_<br />
Q<br />
Fig. 1. Buck Converter with Constant-On-Time control.<br />
R<br />
S<br />
Q<br />
Traditionally, voltage mode control and current mode control have<br />
been employed widely in power management ICs. Next generation<br />
requirements of fast transient response, ease of design, and fast timeto-market<br />
have posted great challenges to power controller providers.<br />
In recent years, constant-on-time (COT) control has gained<br />
tremendous interest from DC-DC power IC suppliers, thanks to its<br />
inherent advantages over traditional control architectures.<br />
Fig. 1 shows a buck converter with constant-on-time control. Unlike conventional<br />
voltage-mode control and current-Mode control that employ an oscillator, an<br />
error amplifier and compensation circuit, a comparator is used in the feedback loop<br />
for COT. At the beginning of each cycle, the IC initiates an on-time period when<br />
the feedback voltage falls below the reference voltage. The high-side MOSFET<br />
stays on for a fixed duration. At the end of on-time, the high-side MOSFET turns<br />
off until the feedback voltage falls below the reference. To provide an interval<br />
for current sense and PFM operation, the controller usually provides a minimum<br />
off-time. Since the error amplifier, compensation circuit, and even oscillator are<br />
eliminated, the COT features simple implementation, easy PFM operation, and<br />
superior transient response.<br />
As a ripple-based control approach in nature, however, COT requires minimum<br />
ripple voltage on output feedback to operate properly. Research in literature has<br />
shown that the instability is due to the phase shift of the capacitive component of<br />
output ripple [ 1-11 ]. If the capacitive ripple magnitude dominates the total output<br />
voltage ripple which consists of resistive equivalent-series-resistance (ESR) ripple,<br />
capacitive ripple, and equivalent-series-inductance (ESL) ripple, double or multiple<br />
pulses per switching cycle may occur, and result in sub-harmonic oscillation at output.<br />
A common practice to address this issue is to use bulk output capacitors with<br />
higher ESR such as electrolytic, OSCON, and POSCAPs.<br />
If the contribution of the ESR ripple surpasses the<br />
V capacitive ripple, the power supply with COT will<br />
IN<br />
be stabilized. The downside is that the output voltage<br />
ripple will increase, which poses another challenge<br />
to power supply design. Driven by increased<br />
V L<br />
X<br />
VO pressure from tight output voltage regulation, cost<br />
and size reduction requirements, power supply<br />
Rt designers have been trying to avoid using the number<br />
of bulk capacitors, and resort to ceramic capacitors.<br />
CO Compared to bulk capacitors, ceramic capacitors<br />
Rb offer significantly lower price, smaller size, and<br />
lower ESR. Importantly, with all-ceramic capacitors<br />
being used as output filters, the output ripple will be<br />
extremely low due to small capacitor ESR. To meet<br />
the minimum ripple requirement of COT all ceramic<br />
www.powerelectronics.com January 2013 | <strong>Power</strong> <strong>Electronics</strong> Technology 27
BUCKconverters<br />
design, a ripple-generating circuit has been<br />
widely utilized. Generally speaking, too big<br />
a ripple will cause large output voltage DC<br />
regulation error and also deteriorate transient<br />
performance, while insufficient ripple<br />
may lead to instability. Therefore, optimal<br />
values for the ripple-generating circuit are<br />
needed to meet minimum ripple voltage<br />
requirement on FB pin while still maintaining<br />
stability.<br />
Ripple-geneRating ciRcuit<br />
Fig. 2 shows a widely employed rippleinjecting-circuit<br />
for COT all-ceramic capacitor<br />
design. This circuit consists of a resistor and two<br />
capacitors. A resistor RX and a capacitor CX are connected<br />
to the two terminals of the inductor. If the values<br />
are chosen correctly, triangle voltage ripple will be generated<br />
on CX which resembles the inductor current ripple.<br />
The triangle voltage ripple will then be injected to the FB<br />
pin. Capacitor CD blocks the DC component of voltage<br />
on CX so that ideally only the AC ripple will pass through<br />
to reach the FB pin. In practice, the desired ripple voltage<br />
at FB pin is usually given. The ripple-generating circuit<br />
design can be started with selection of RX and CX. In the<br />
s-domain, the voltage on CX is:<br />
(1)<br />
Where:<br />
IL = Inductor current<br />
L = Inductance<br />
DCR = Direct-Current-Resistance<br />
of the inductor<br />
Inductor current, IL, consists of<br />
DC component that is the load current<br />
and AC component, which is<br />
the ripple current. Manipulating<br />
Equation (1) and eliminating the DC<br />
component of IL leads to the equa-<br />
Fig. 3. Simulation results for Ripple-generating-<br />
circuit with two different cD values. For two top<br />
waveforms, Waveform 1 in red is 1.216V and<br />
Waveform 2 is 1.204V. For two bottom waveforms,<br />
Waveform 1 in red is the FB voltage for cD of<br />
1000pF, with peak-peak voltage of 11mV. Waveform<br />
2 in green is for cD of 220pF, with peak-peak volt-<br />
age of 6mV. the blue waveform in the middle is the<br />
11mV ripple voltage on cx.<br />
V_Cx/mV<br />
Vfb/mV<br />
1.22<br />
1.218<br />
1.216<br />
1.214<br />
1.212<br />
1.21<br />
1.208<br />
1.206<br />
1.204<br />
1.202<br />
1.2<br />
Vout/V 1.222<br />
20<br />
18<br />
16<br />
14<br />
12<br />
10<br />
Min Off<br />
Time<br />
1<br />
On Time<br />
One Shot<br />
– +<br />
tion for the ripple voltage on Cx:<br />
Where:<br />
V CX(PP) = Ripple voltage on Cx<br />
I L(PP ) = Inductor peak-peak current ripple<br />
CX is usually picked at a value in between 0.1 µF<br />
and 1 µF. When it comes to the selection of CD, a common<br />
assumption is that the ripple voltage on CX will be<br />
coupled equally to FB through CD, i.e. V CX(PP) is equal to<br />
injected ripple voltage at FB. As such, its value is chosen<br />
arbitrarily to some degree.<br />
To verify if the above assumption is valid, a closed-loop<br />
28 <strong>Power</strong> <strong>Electronics</strong> Technology | January 2013 www.powerelectronics.com<br />
OR<br />
FB Vref<br />
2<br />
R<br />
S<br />
Q<br />
_<br />
Q<br />
V IN<br />
612<br />
610<br />
608<br />
1<br />
606<br />
604<br />
602<br />
600<br />
598<br />
11 mV<br />
2<br />
6 mV<br />
99.98 99.982<br />
time/ms<br />
99.984 99.986 99.988 99.99 99.992 99.994 99.996 99.998 100<br />
V X<br />
R X<br />
1.216 V<br />
1.204 V<br />
11 mV<br />
L<br />
C d<br />
DCR<br />
Fig. 2. Ripple-generating-circuit for Buck converter with constant-On-time control.<br />
C X<br />
R t<br />
R b<br />
V O<br />
C O<br />
(2)
model of COT controlled buck converter<br />
was built in Simplis. Simulation<br />
is done using two different CD values,<br />
220pF and 1000pF, while the other<br />
parameters are kept the same. Fig. 3(a)<br />
shows the simulation results of the ripple<br />
voltages on CX and FB pin. The top<br />
window is the ripple voltage on CX,<br />
which is 11mV. Waveform 1 in red in<br />
the bottom window is the FB voltage for<br />
CD of 1000pF, with peak-peak voltage<br />
of 11mV, while Waveform 2 in green in<br />
the same window is for CD of 220pF,<br />
with peak-peak voltage of 6mV.<br />
It was found that different CD values<br />
can result in different ripple magnitudes,<br />
even different waveform shapes on the<br />
FB pin. Therefore, the ripple voltage on<br />
CX will not necessarily be coupled to FB<br />
pin. Fig. 3 (b) shows the output voltages.<br />
Waveform 1 in red in the top window is<br />
1.216V and Waveform 2 is 1.204V. The<br />
CD value difference alone can result in<br />
a DC regulation difference of 12mV in<br />
this specific case. Therefore, if CD is not chosen properly,<br />
the ripple voltage on FB pin can be either insufficient,<br />
which leads to instability, or too big, which not only adds<br />
DC regulation error at output but also degrades transient<br />
performance.<br />
To better understand the effects of the CD on the FB<br />
voltage, it is worthwhile to examine the voltage on CD. If<br />
we approximate ICD(PP) as a triangle, the equation for<br />
VCD(PP) is analogical to the equation for output voltage<br />
ripple which is<br />
.<br />
The ripple voltage on CD can be approximated as:<br />
(3)<br />
Where:<br />
V CD(PP) = Ripple voltage on CD<br />
I CD(PP) = Ripple current across capacitor<br />
CD<br />
FSW = Switching frequency of the<br />
converter<br />
The output capacitance value is usually<br />
large, so you can consider the<br />
output as a low impedance at high frequencies.<br />
By superposition of the ripple<br />
contributed by ripple current on CD<br />
Vout/V<br />
V_Cd/mV<br />
V_Cx/mV<br />
Vfb/mV<br />
1.222<br />
1.2215<br />
1.221<br />
1.2205<br />
1.22<br />
1.2195<br />
1.219<br />
1.2185<br />
1.218<br />
712<br />
711.5<br />
711<br />
710.5<br />
710<br />
709.5<br />
709<br />
708.5<br />
110<br />
105<br />
100<br />
95<br />
90<br />
620<br />
615<br />
610<br />
605<br />
600<br />
99.98 99.982 99.984 99.986 99.988 99.99 99.992 99.994 99.996 99.998<br />
time/ms<br />
and ripple voltage at output, the ripple voltage on FB pin is:<br />
Based on Kirchhoff’s voltage law, the relationships of<br />
V CX(PP) , V CD(PP) , V O(PP) , and V FB(PP) are:<br />
By examining Equation (5) we found that if V CD(PP) is<br />
made equal to V O(PP) , V FB(PP) will be equal to Vcx(pp) ,<br />
which means that the ripple voltage at FB pin will resemble<br />
the triangle voltage ripple on CX under a specific<br />
condition. Therefore, if an optimal value of CD is found<br />
so that the voltage ripple on CD resembles output voltage<br />
ripple, the FB voltage ripple will<br />
be purely resistive and triangle, hence<br />
stability can be achieved under most<br />
conditions. The output ripple, CX<br />
voltage ripple, and other parameters<br />
except I CD(PP) and CD are known or<br />
obtainable from 4. Therefore, replacing<br />
V CD(PP) in Equation (3) with<br />
V O(PP) and inserting the expression<br />
of I CD(PP) into Equation (4) leads to<br />
an optimal CD value that makes FB<br />
ripple a triangle voltage:<br />
www.powerelectronics.com January 2013 | <strong>Power</strong> <strong>Electronics</strong> Technology 29<br />
V O<br />
Vcd pp<br />
Vcx pp<br />
Vfb pp<br />
Fig. 4. Simulation results for ripple-generating circuit with optimal CD value.<br />
Fig. 5. FAN2306 Evaluation Board<br />
(5)<br />
(4)
BUCKconverters<br />
(6)<br />
If the number of output ceramic capacitors is big<br />
enough, the output voltage ripple will be extremely low.<br />
As a result, the injected ripple V X(PP) should be much<br />
larger than the capacitive ripple on FB pin, so Equation (6)<br />
can be further simplified to:<br />
With the discovery of the optimal value of CD, it will<br />
appear as if the capacitive component on the feedback pin is<br />
filtered out. As a result, the ripple-generating circuit can be<br />
designed with minimum required ripple for stability, which<br />
maximizes transient performance and minimizes output<br />
DC regulation error. The design procedure of the ripplegenerating<br />
circuit can be summarized as the following:<br />
1. Provide all power stage parameters.<br />
2. Determine desired injected ripple at FB pin based on<br />
controller requirements. This ripple is approximately<br />
equal to the ripple voltage on CX if the ripple circuit is<br />
designed properly.<br />
3. Pick a value for CX and calculate the value for RX by<br />
Equation (2).<br />
4. Optimal value for CD can be calculated by Equation (6).<br />
The output DC regulation error can be approximated as:<br />
Simulation and ExpErimEntal rESultS<br />
The simulation model is built to verify the design approach<br />
for the ripple-generating circuit. The results are shown<br />
in Fig. 4. The waveforms from top to bottom are VO,<br />
V CD(PP) , V CX(PP) , and V FB(PP) . It is found that with optimal<br />
CD value, the ripple voltage on CD resembles the<br />
ripple voltage on output, hence the ripple voltage on the<br />
FB pin looks purely triangular and resistive! Moreover, the<br />
targeted injected ripple voltage (21 mV) is achieved at the<br />
FB pin.<br />
An evaluation board was built to verify the ripplegenerating<br />
circuit as shown in Fig. 5. The controller is<br />
FAN2306, which is a constant-on-time controller from<br />
Fairchild Semiconductor. The circuit parameters are:<br />
V IN = 12V<br />
V O = 1.2V<br />
F SW = 500kHz<br />
L O = 1µH<br />
C O = 4x47µF MLCC<br />
R T = 10kΩ<br />
R B = 10kΩ<br />
(7)<br />
(8)<br />
Fig. 6. Experimental results<br />
top trace in green is the FB pin voltage.<br />
Yellow trace in the middle is the output ripple voltage<br />
Bottom trace in pink is the switching node waveform<br />
RX = 1kΩ<br />
CX = 0.1µF<br />
For the targeted 22mV ripple generated at FB pin, the<br />
calculated optimal CD is about 335pF. A 330pF standard<br />
value is chosen on the evaluation board for CD.<br />
The experimental results are shown in Fig. 6. The top<br />
trace in green is the FB pin voltage. The yellow trace in the<br />
middle is the output ripple voltage. And the bottom trace<br />
in pink is the switching node waveform. The measured FB<br />
ripple voltage is in triangle shape with magnitude of about<br />
24.4mV. It matches the theory fairly well.<br />
REFERENCES<br />
[1]Y. Lin, C. Chen, D. Chen, B. Wang, “A novel ripple-based constant on-time control<br />
with virtual inductance and offset cancellation for DC power converters,” IEEE<br />
Energy Conversion Congress and Exposition, pp. 1244-1250, Sep. 2011.<br />
[2]C. Chen. D. Chen, C. Tseng, C. Tseng, Y Chang, K. Wang, “A novel ripplebased<br />
constant on-time control with virtual inductor current ripple for Buck converter<br />
with ceramic output capacitors,” in IEEE Applied <strong>Power</strong> <strong>Electronics</strong> Conference,<br />
2011, pp. 1488-1493.<br />
[3]J. Wang; J. Xu; B. Ba, “Analysis of Pulse Bursting Phenomenon in Constant-On-<br />
Time-Controlled Buck Converter,” IEEE Transactions on Industrial <strong>Electronics</strong>, vol.<br />
58, Issue. 12, pp. 5406-5410, 2011.<br />
[4]K. Cheng; F. Yu; P. Mattavelli, F. Lee, “Characterization and performance comparison<br />
of digital V2-type constant on-time control for buck converters,” IEEE 12th<br />
Workshop on Control and Modeling for <strong>Power</strong> <strong>Electronics</strong>, pp. 1-6, 2010.<br />
[5]R. Miftakhutdinov, “Compensating DC/DC Converters with Ceramic Output<br />
Capacitors,” Texas Instruments <strong>Power</strong> Supply Design Seminar, 2004/05, http://<br />
www.smps.us/Unitrode.html.<br />
[6] F. Yu, F. Lee, “Design oriented model for constant on-time V2 control,” IEEE<br />
Energy Conversion Congress and Exposition, pp. 3115-3122, 2010.<br />
[7] J. Wang, B. Bao, J. Xu, G. Zhou, W. Hu, “Dynamical Effects of Equivalent<br />
Series Resistance of Output Capacitor in Constant On-Time Controlled Buck<br />
Converter,” IEEE Transactions on Industrial <strong>Electronics</strong>, pp. 1, 2012.<br />
[8]R. Redl, S. Jian, “Ripple-Based Control of Switching Regulators—An Overview,”<br />
IEEE Transactions on <strong>Power</strong> <strong>Electronics</strong>, Vol. 24, pp. 2669-2680, 2009.<br />
[9]Y. Lee, W. Lai, W. Pai, K. Chen, M. Du, S. Cheng, “Reduction of equivalent<br />
series inductor effect in constant on- time control DC-DC converter without ESR<br />
compensation,” IEEE International Symposium on Circuits and Systems, pp. 753-<br />
756, 2011.<br />
[10]T. Shuilin, K. Cheng, F. Lee, P. Mattavelli, “Small-signal model analysis and<br />
design of constant-on-time V2 control for low-ESR caps with external ramp compensation,”<br />
IEEE Energy Conversion Congress and Exposition, pp. 2944-2951, 2011.<br />
[11]T. Qian, “Sub-Harmonic Analysis for Buck Converters with Constant On-Time<br />
Control and Ramp Compensation,” IEEE Transactions on Industrial <strong>Electronics</strong>,<br />
pp. 1, 2012.<br />
[12]FAN2306 datasheet, available at www.fairchildsemi.com.<br />
30 <strong>Power</strong> <strong>Electronics</strong> Technology | January 2013 www.powerelectronics.com
designfeature<br />
Kim Gauen and PhiliPPe duPuy, Freescale Semiconductor<br />
Intelligent <strong>Power</strong> Switches<br />
for 24 V Vehicular Systems<br />
A family of smart high side<br />
devices for 24V applications<br />
are compatible in footprint<br />
and software to address loads<br />
from 1A to 12A DC. These dual<br />
high side, intelligent power<br />
switches are intended for<br />
trucks and buses that use 24V<br />
batteries.<br />
Automotive body electronics modules<br />
routinely use intelligent<br />
power switches to control<br />
loads such as lamps, LEDs,<br />
solenoids and motors. The<br />
trend to replace relays with<br />
solid state switches began more<br />
than a decade ago when system requirements<br />
mandated using solid state switches. The<br />
need to PWM the lamps to extend lamp Fig. 1. <strong>Power</strong> Switch ICs are housed in the 23 lead,<br />
lifetimes, requirements for dimming such as 12 mm by 12 mm, PQFN package.<br />
daytime running lamps, the desire to reduce<br />
mechanical noise, demands to shrink module size while increasing functionality,<br />
the need for accurate diagnostics, etc., all worked against using relays.<br />
Since those early days, the market has exploded with specialized devices designed<br />
to meet the many demanding and sometimes unique requirements of this application.<br />
Many years of development have produced today’s low cost devices that<br />
are efficient, safe, flexible, reliable, robust and fault tolerant. Now, those same<br />
advances are being extended to intelligent power switches designed for the more<br />
demanding requirements of 24 V systems. Requirements of a solid state switch<br />
for 24 V truck and bus systems must consider what we have already learned from<br />
Table 1. ComParison of 12 and 24 V<br />
sysTem baTTery VolTaGe requiremenTs<br />
12 V sysTem 24 V sysTem<br />
Operating voltage range 4 V to 20 V 8 V to 32 V<br />
Under voltage 4.1 V typ. (4.5 V max) 6 V<br />
Over voltage 32 V typ. (28 V min) 36 V min<br />
Supply voltage clamp 47 V 58 V<br />
* Fast negative transient pulse (1) -25 V to -100 V **-150 V to -600 V<br />
*Fast positive transient pulse (2a) +50 V +50 V<br />
*Burst negative pulses (3a) -150 V -200 V<br />
*Burst positive pulses (3b) +100 V +200 V<br />
*Cranking pulse (4) 4.5 or 5.0 V 8 V<br />
*Load dump (5b) 41 V 58 V<br />
Reverse battery -16 V -32 V<br />
*Values in parentheses refer to pulse types described in ISO7637-2 standard **OEM dependent<br />
www.powerelectronics.com January 2013 | <strong>Power</strong> <strong>Electronics</strong> Technology 31
powerswitches<br />
MCU<br />
INTERFACE<br />
Functional Internal Block Description<br />
POWER SUPPLY<br />
internal regulator<br />
MCU INTERFACE and<br />
OUTPUT CONTROL<br />
SPI INTERFACE<br />
PARALLEL CONTROL<br />
INPUTS<br />
PWM CONTROLLER<br />
SELF-<br />
PROTECTED<br />
HIGH SIDE<br />
SWITCHES<br />
HSO-HS1<br />
Fig. 2. Internal functional block diagram of this intelligent power switch family.<br />
the use of solid state switches in 12 V systems. Many of<br />
the requirements of 12 and 24 V systems are similar.<br />
Perhaps the primary requirement is low cost. Here,<br />
the entire system cost as well as the device cost is of<br />
interest. This includes the cost of thermal management,<br />
MCU overhead and pin count, PCB area for mounting<br />
and routing, additional circuitry needed for diagnostics<br />
and fault management, protection components such as<br />
capacitors needed to suppress voltage transients, etc. To<br />
minimize system costs associated with managing power,<br />
the latest devices have very low on-resistances to reduce<br />
power dissipation. Additionally, their SPI interface makes<br />
many control and diagnostic features possible and reduces<br />
MCU overhead and pin count. The SPI interface also greatly<br />
reduces routing complexity and saves PCB area.<br />
l OCH1<br />
l OCH2<br />
lOCM1 Load lOCM2 Current<br />
l OCL1<br />
l OCL2<br />
tOCM1 tOCM2 tOCH1 tOCH2 Static multi-stage overcurrent protection<br />
profile protects lamps without shutting down<br />
the supply during inrush current<br />
Fig. 3. MC10XS4200 over current threshold profiles.<br />
Next, the system must be safe. Exterior lighting is a<br />
critical safety feature, so the intelligent driver must be<br />
compatible with the module’s overall fault management<br />
and failsafe strategy. The power switches must respond<br />
to any failsafe condition and autonomously activate safety<br />
critical lamps or other loads.<br />
FLEXIBILITY REQUIRED<br />
Third, the system must be flexible to accommodate variations<br />
in the number, size and types of loads. For example, lighting<br />
loads are now often a varying mix of incandescent lamps<br />
and LEDs. Lamp and LED power levels, start-up behavior<br />
and fault thresholds differ considerably, but the power<br />
switch might be required to drive either type. PWMing of<br />
incandescent lamps has become quite common, because<br />
it allows limiting lamp power at elevated battery voltage,<br />
which can greatly increase lamp lifetime. It also allows<br />
dimming of lamps for daytime running lights or “theater<br />
dimming,” a slow increase or decrease in light output.<br />
Fourth, the power devices must be fault tolerant. The<br />
automotive electrical environment is notorious for its<br />
number of possible faults and the need to tolerate them.<br />
Shorts can be “soft” or “hard.” They can be intermittent.<br />
And, the output can be shorted to battery as well as to<br />
ground. The battery may be reversed. Many of these faults<br />
must be detected and reported, even though the current<br />
magnitude of the load might vary with load type and the<br />
state of the load.<br />
Fifth, the power switches must be efficient. Better<br />
efficiency, of course, is highly desired to improve overall<br />
vehicle efficiency. A second and very important benefit<br />
of higher device efficiency is that more efficient devices<br />
generate less power in their module. Most modules have<br />
Time Time<br />
Dynamic overcurrent protection window<br />
protects DC motors without shutting down<br />
the supply during short stall-periods<br />
32 <strong>Power</strong> <strong>Electronics</strong> Technology | January 2013 www.powerelectronics.com<br />
l OCH1<br />
l OCH2<br />
l OCL1<br />
l OCL2<br />
tOCM1 tOCM2 tOCH1 tOCH2
plastic housings and often the printed<br />
circuit board provides the only heatsinking<br />
for the power components. Since<br />
a control module may require many<br />
outputs, it is paramount that each<br />
driver minimizes its contribution to<br />
the module’s thermal load.<br />
Finally, the system must meet many<br />
immutable requirements of automotive<br />
body electronics. For example, the<br />
vast majority of the loads are ground<br />
referenced and must be controlled by a<br />
“high side switch”. Some loads must be<br />
PWMed at a specific frequency. Ambient<br />
temperatures and power density are high<br />
while the thermal environment is often poor. Quiescent<br />
current must be low to minimize battery drain when the<br />
vehicle is parked. Thermal cycling, radiated and conducted<br />
emissions and susceptibility, ESD and mechanical stresses<br />
are other requirements that have to be considered during<br />
device as well as module and system development.<br />
Besides the obvious requirement to manage a higher system<br />
voltage and its new set of transients, a 24 V system is likely to<br />
have a longer and more severe service life, a greater variety<br />
of load types and sizes, more numerous loads and longer<br />
wiring harnesses. Each of these is discussed briefly below.<br />
HigHer operating and transient voltages<br />
Vehicular voltage transient specifications are more demanding<br />
in 24 V systems. Table 1 compares the various ISO7637-<br />
2 transients for 12 and 24 V systems. Operating voltage<br />
ranges are also given.<br />
very HigH quality and reliability<br />
Vehicles using 24 V systems are often commercial or<br />
heavy duty vehicles. In terms of reliability, mission profile,<br />
ambient conditions, etc., the requirements of 24 V<br />
systems exceed those of their 12 V counterparts. Table<br />
2 shows that heavy duty vehicles typically have a shorter<br />
service life but a much more demanding operating profile.<br />
For example, typical requirements for 24 V systems are:<br />
• Lifetime expectancy of over 30,000 hrs or 1.5 million km<br />
Table 2. OperaTing prOfiles<br />
Of 12 and 24 V sysTems<br />
Car (12V) bus (24V) TruCk (24V)<br />
Lifetime (years) 15 to 19 15 10 to 15<br />
Annual Activation<br />
Time (hours per year)<br />
> 500 > 2500 > 4000<br />
Total kilometers (km) 240K 800K 3Mio<br />
Besides the obvious<br />
requirement to<br />
manage a higher<br />
system voltage<br />
and its new set of<br />
transisents, a 24 V<br />
system is likely to<br />
have a longer and<br />
more severe service<br />
life.<br />
• Operating profile for trucks up to<br />
300,000km/year<br />
• Ambient operating temperature range<br />
of -40°C to 125°C<br />
• Very low failure rate to minimize<br />
service disruption and vehicle down<br />
time<br />
• System must be very robust with respect<br />
to vehicle transients and load faults<br />
• Components must be robust with<br />
respect to wear out mechanisms<br />
More loads and More types of loads<br />
Lighting loads predominate in most automotive<br />
body control modules. While 24<br />
V body control modules may control even more lighting<br />
loads, they also tend to control many solenoids and motors<br />
as well. They also provide power to other modules. In<br />
broad terms, here are some of the features of their loads<br />
and how they differ from those of 12 V systems:<br />
• Higher nominal power to service a larger vehicle<br />
• Higher inductance of inductive loads<br />
• Systems have more loads than 12 V systems and more<br />
of those loads are motors and solenoids<br />
• Motors are often PWMed @ ~1 kHz from 5% to 100%<br />
whereas lighting is PWMed at 100 to 200 Hz<br />
Wiring Harness lengtH<br />
Wire harnesses for a 24 V system are often much longer<br />
than in that of a typical passenger vehicle. The load can be<br />
up to 20 meters from a module within the vehicle, and up<br />
24 v faMily of dual, HigH side intelligent sWitcHes<br />
Semiconductor manufacturers are developing intelligent high<br />
side switches for the 24 V vehicle market. Table 3 lists the<br />
www.powerelectronics.com January 2013 | <strong>Power</strong> <strong>Electronics</strong> Technology 33<br />
V DD<br />
I/O<br />
I/O<br />
SCLK<br />
CSB<br />
SI<br />
I/O<br />
MCU<br />
SO<br />
I/O<br />
I/O<br />
I/O<br />
A/D<br />
A/D<br />
GND<br />
V DD<br />
MC10XS4200<br />
V PWR<br />
VDD VPWR<br />
CLOCK<br />
FSB<br />
SCLK HS0<br />
CSB<br />
SO<br />
RSTB<br />
SI<br />
HS1<br />
IN0<br />
IN1<br />
CONF0<br />
CONF1<br />
FSOB<br />
SYNC<br />
CSNS<br />
GND<br />
M<br />
LOAD<br />
LOAD<br />
fig. 4. simplified application diagram of the Mc10Xs4200 that can drive a 6 a<br />
load per channel.
powerswitches<br />
TablE 3. FREESCalE’S 24 V iNTElligENT powER SwiTChES<br />
DEViCE<br />
No.<br />
ouTpuTS<br />
oN-RESiSTaNCE<br />
pER ouTpuT<br />
loaD CuRRENT<br />
pER ChaNNEl<br />
MC06XS4200 2 6 mΩ 9A Bank of lamps, small motors<br />
MC10XS4200 2 10 mΩ 6A Larger lamps, small motors<br />
MC20XS4200 2 20 mΩ 3A Smaller lamps, LEDs<br />
first components in Freescale Semiconductor’s offering.<br />
Each of these devices is housed in the 23 lead, 12 mm by<br />
12mm, PQFN package (Fig. 1). This package was developed<br />
for intelligent high side switches and features excellent<br />
thermal conductivity, a small footprint and high reliability.<br />
Its high pin count allows SPI control, sophisticated fault<br />
diagnostics and fault management and failsafe features. These<br />
devices have the same pinout and feature set except for<br />
those features related to the on-resistance and its associated<br />
current and energy capacity. Fig. 2 shows the internal<br />
functional block description of this family of intelligent<br />
power switches.<br />
numerous features<br />
Each device has a vast array of features, which include:<br />
• Dual, low on-resistance, self protected, high side MOSFETs<br />
• 16-bit SPI interface for device configuration, control<br />
and diagnostics; 3.3V and 5V compatible<br />
• Configurable to drive incandescent lamps, LEDs, DC<br />
motors or solenoids<br />
• Independent control of each channel by any of the following:<br />
• Internally generated, PWM clock autonomous operating<br />
mode<br />
• External clock-signal, modulated or not<br />
• Two dedicated direct inputs<br />
• Fail-safe operation mode, allowing continued basic control<br />
if communication with the master device is lost<br />
• Programmable over current profile to provide protection<br />
without avoid false over current faults during lamp inrush<br />
• Flexible current sensing allows monitoring either output<br />
separately in synchronous & asynchronous mode<br />
• Controlled output-voltage slew-rates (individually programmable)<br />
for EMC compliance.<br />
• Parallel bit to control a higher current load<br />
An example of the programmability is the ability to tailor<br />
the overcurrent profile for the expected load. Fig. 3 shows<br />
the possible over current profiles that can be chosen for a<br />
particular load. Through a hardware pin configuration, the<br />
device offers either a static profile suited for loads having<br />
an inrush current (like lamps) or a dynamic profile adapted<br />
for inductive loads (like DC motors). Any load current<br />
excursion beyond the over<br />
current profile creates an over<br />
current fault and immediately<br />
TaRgETED loaDS turns off the output thereby<br />
reducing stress in the switch,<br />
the harness, the supply and<br />
the load. An automatic retry<br />
is embedded in the device to<br />
allow a proper activation of<br />
the load even in case of an<br />
intermittent short circuit event.<br />
This allows minimizing the device’s aging under repetitive<br />
overstress conditions to reach 10x better robustness than<br />
for standard solutions.<br />
feWer components and I/os<br />
The ability to program the intelligent switch through an<br />
SPI communications interface not only gives the systems<br />
designer an exhaustive load protection and diagnostics,<br />
but it also reduces the number of MCU I/Os and discrete<br />
components. This is particularly important for many 24<br />
V vehicle applications, for which more than 20 power<br />
outputs are common to control an increasingly vast<br />
repetoire of functions as vehicles continue to add safety<br />
and convenience features.<br />
Listing the benefits of using an SPI controlled device<br />
can be eye opening. As an example, consider a control<br />
module that has twenty six 1 to 2A loads. The user<br />
can control these loads using 13 dual switches such as<br />
Freescale’s MC10XS4200 intelligent switch, or 26 single<br />
output drivers in a TO-252 style package. Freescale’s switch<br />
is a clear choice.<br />
The MC10XS4200 is a highly versatile 24 V intelligent<br />
switch. Fig. 4 shows a typical application circuit for the<br />
MC10XS4200 power switch, which can drive a 6 A load<br />
per channel. The dual channel, high-side intelligent switch<br />
has a complete range of I/O, clock, sync, and other functions<br />
to control large lamps and small motors typically<br />
encountered in vehicles.<br />
Given that LEDs are increasingly part of the load mix<br />
in today’s vehicles, the current sense accuracy requirements<br />
are much more demanding. This in turn requires<br />
the addition of op amps and sense resistors. Using an SPI<br />
enabled device such as the MC10XS4200 power switch<br />
brings out most of the functionality within the device.<br />
For the system designer, this versatility results in far fewer<br />
external components, greatly reduced and simplified routing<br />
of control signals, less PCB area, and a more flexible<br />
system.<br />
REFERENCES<br />
[1] ISO7637-2 Road vehicles — Electrical disturbance by conduction<br />
and coupling — Part 2: Vehicles with nominal 12 V or 24 V<br />
supply voltage.Electrical transient conduction is along supply lines.<br />
34 <strong>Power</strong> <strong>Electronics</strong> Technology | January 2013 www.powerelectronics.com
PETinnovations<br />
HAN S. LEE, Delphi Automotive Systems, LLC, TIM MCDONALD, International Rectifier, and LAURA MARLINO,<br />
Oak Ridge National Laboratory<br />
Contributors: Gary Eesley, Carl Berlin, Erich Gerbsch, Aditya Neelakantan, Delphi Automotive Systems, LLC; Michael A.<br />
Briere (ACOO Enterprises, LLC for IR), Naresh Thapar, Kevin Linthicum, Michael Brodsly, International Rectifier; Dianne Bull,<br />
Charles Britton, Andrew Wereszczak, Zhenxian Liang, Madhu Chinthavali, Oak Ridge National Laboratory<br />
GaN on Silicon-based <strong>Power</strong> Switch<br />
in a Sintered, Dual-side Cooled Package<br />
SPONSORED BY the U.S. Department of Energy,<br />
under the Advanced Research Projects Agency<br />
for Energy (ARPA‐E), Delphi Automotive,<br />
International Rectifier (IR) and Oak Ridge<br />
National Laboratory have collaborated to produce<br />
600V-rated GaN on Silicon HEMTs (based on IR’s<br />
GaNpowIR ® platform) with sintered packaging interconnects<br />
(using Delphi’s power semiconductor device<br />
package featuring dual-side cooling) capable of meeting<br />
the demanding power processing, environmental, power<br />
density and efficiency requirements for auxiliary and traction<br />
power in advanced hybrid and electric vehicles. We<br />
will detail construction, performance, initial reliability and<br />
modeled benefits in automotive traction application compared<br />
to existing IGBT solutions.<br />
GANPOWIR¨ PERFORMANCE<br />
The GaN-based HEMT technology used in the current<br />
effort leveraged the use of IR’s GaNpowIR ® development.<br />
This included use of depletion-mode GaN on Silicon (Si)<br />
HEMTs configured in cascode connection to a low-voltage,<br />
silicon power FET. The 600V GaN devices were fabricated<br />
on 6-inch GaN on Silicon wafers and processed in a standard<br />
high volume silicon fabrication facility. Likewise, the lowvoltage,<br />
silicon FET used was optimized for cascoded operation<br />
with the GaN HEMTs and also manufactured by IR.<br />
Fig. 1 shows the typical measured room-temperature<br />
output characteristics of a 600V GaN on Si based HEMT<br />
with an active area of 8 mm 2 and gate width of 278<br />
mm, cascoded with a low-voltage silicon FET in a high<br />
performance dual-side cooled package with sintered interconnects<br />
(Fig. 3a and 3b). As shown, the normally-off<br />
cascoded device demonstrates well behaved current handling<br />
capability with saturation occurring at about 80 A,<br />
providing ~1000 A/cm 2 of current density, significantly<br />
higher than that typically provided by the incumbent<br />
IGBT technology. Fig. 2 shows the normally-off transfer<br />
characteristics of a typical cascoded device at both room<br />
temperature and 150°C. As shown, threshold voltage<br />
(extrapolated zero drain current intercept with the x-axis)<br />
is approximately 5.4 V at room temperature and approximately<br />
4.4 V at elevated temperature. This demonstrates<br />
a substantial advantage of the cascode switch design over<br />
other normally-off GaN devices: gate drive requirements<br />
are set by the low-voltage FET and not by the GaN HEMT.<br />
Therefore, existing gate drivers can be used, so no costly<br />
customization or redesign is required.<br />
Further work is ongoing to fabricate much larger devices<br />
(gate width = 1320 mm, active area = 37.5 mm 2 ). These<br />
GaN HEMTs yielded at initial electrical test and will be<br />
demonstrated in a multi-kilowatt inverter by Delphi.<br />
DUAL-SIDED COOLING, SINTERED METAL INTERCONNECT<br />
A schematic representation of the cascode configured package<br />
is shown in Fig. 3. Fig. 3(a) shows the electrical connection<br />
and defines the gate, source and drain of the packaged<br />
device. Fig. 3(b) shows the mechanical layout in the package<br />
to achieve the cascode configuration. Fig. 3(c) shows the<br />
Output, 25 °C<br />
www.powerelectronics.com January 2013 | <strong>Power</strong> <strong>Electronics</strong> Technology 35<br />
I D (A)<br />
90<br />
80<br />
70<br />
60<br />
50<br />
40<br />
30<br />
20<br />
10<br />
15 V 8 V 7.5 V 7 V 6.5 V<br />
0<br />
0 2 4 6 8 10 12<br />
V DS (V)<br />
Fig. 1. Measured output characteristics of a 600 V rated GaN on Si based HEMT<br />
with an active area of 8 mm 2 and a gate width of 278 mm, cascoded with a low-<br />
voltage silicon FET, in a dual-side cooled package, at room temperature.
PETinnovations<br />
packaged device. From a user’s point of view, the packaged<br />
device is a normally-off device.<br />
Both the top cap and the bottom substrate of the package<br />
are DBC substrates for enabling dual-side cooling. For power<br />
devices, dual-side cooling offers a lower thermal resistance<br />
when comparing to a typical wire-bond packaged device,<br />
and thereby provides more efficient heat dissipation from<br />
the packaged devices. From ANSYS simulations, the thermal<br />
resistance of the package was projected to be 0.47°C/W<br />
when both sides were liquid-cooled and 0.57°C/W when<br />
only the bottom substrate is liquid-cooled.<br />
For dual-side cooling, both sides of the die were sintered<br />
to the substrate. To check the bond strength of the sintered<br />
die, metallized silicon pieces were tested. A silicon wafer<br />
was metalized on both sides of the wafer with front and<br />
back side metals identical to the metals used on the GaN<br />
on Silicon HEMT and silicon FET devices. This metallized<br />
wafer was then diced into 5 x 5 mm squares for the test.<br />
Silver paste was screen printed on the back side of the<br />
DBC substrates, using five circular dots, 1 mm in diameter.<br />
Both gold and silver-plated DBC substrates were used. The<br />
locations of the five dots included four dots centered at the<br />
corners of a 3 x 3 mm square and the fifth dot located at<br />
the center of the square. The 5 x 5 mm metalized silicon<br />
piece was positioned and centered on top of the five dots.<br />
The attached sets were sintered and then underwent a<br />
temperature cycle (TC) test to check the TC effect on<br />
the bond strength. The TC test ramped the temperature<br />
between -40°C and 135°C with 30 minutes ramping up,<br />
35 minutes ramping down and soaking 5 minutes at the<br />
end temperatures.<br />
To make sure the effect of sintering pressure on the<br />
thermal cycles could be observed, two different pressures<br />
(High and Low) were used in the sintering process. After<br />
sintering the pieces at 260°C for 5 minutes, several pieces<br />
of each condition were shear tested, to provide a precycling<br />
baseline. The rest of the samples were put into<br />
a chamber for the temperature cycling test. Shear stress<br />
measurements were performed after each 250 temperature<br />
cycles, until 1250 cycles had been completed.<br />
Fig. 4 shows the shear strength<br />
of the bonded silicon chips to the<br />
substrates during the temperature<br />
cycling test. Each error bar represents<br />
plus or minus one standard<br />
deviation of the m easured values.<br />
The data show that after 1000<br />
temperature cycles, there is no<br />
significant shear strength degradation<br />
in the samples sintered<br />
with High Pressure. Even at the<br />
end of tests (1250 cycles); measured<br />
shear strength is still higher<br />
Gate<br />
Drain<br />
GaN on<br />
Silicon<br />
HEMT<br />
Si<br />
MOSFET<br />
than 50 MPa. The samples that used Low Pressure in the<br />
sintering process had their shear stress degrade 30% to 50%<br />
by the end of thermal cycle test.<br />
Once initial sintering conditions were determined, cascoded<br />
GaN on Si HEMT (active area = 8 mm 2 , gate width =<br />
278 mm) and Si FET devices were packaged with dual-side,<br />
sintered silver interconnects. Initial long-term intermittent<br />
operating life (IOL) testing (power cycling) is ongoing, to<br />
compare the reliability of the sintered interconnect technology<br />
used in the high performance packages to that of the soldered<br />
interconnect packaging typically used in the industry.<br />
In prior work, IOL testing on soldered technology has shown<br />
that failure in power modules occurs due to bond-wire liftoff<br />
typically starting at about 10,000 cycles; secondarily, the die<br />
to package solder joint fails at about 40,000 cycles (at delta-<br />
T of approximately 100°C) [1] . Fig. 5 shows the change in<br />
RDS (ON) measured initially and again after 18,000 cycles<br />
for several cascoded sintered devices. Devices were stressed<br />
at a delta-T of 100°C with a cycle time of approximately<br />
six minutes. As can be seen, there is relatively little change<br />
in performance and no failures have been observed out<br />
through 18,000 cycles.<br />
36 <strong>Power</strong> <strong>Electronics</strong> Technology | January 2013 www.powerelectronics.com<br />
I D (A)<br />
100<br />
10<br />
1<br />
0.1<br />
Transfer<br />
150 °C<br />
25 °C<br />
0.01<br />
0 1 2 3 4 5<br />
V (V)<br />
GS<br />
6 7 8 9 10<br />
Fig. 2. Measured transfer characteristics of a 600 V rated GaN on Si based HEMT<br />
with an active area of 8 mm 2 and a gate width of 278 mm, cascoded with a low-<br />
voltage silicon FET, in a dual-side cooled package, at room temperature and 150°C.<br />
Interconnector<br />
Si Die<br />
Bottom<br />
Substrate<br />
GaN Die<br />
Top Cap<br />
Source<br />
Substrate<br />
(a) (b) (c)<br />
Fig. 3. The GaN and silicon die are packaged in a cascode connection. The device exhibits normally-off functionality.<br />
Drain<br />
Gate<br />
Source
These preliminary results are in line with previously published<br />
data (for sintered interconnect packaging) and demonstrate<br />
the high current GaN devices fabricated in this work<br />
have longer useful life than traditional IGBT modules which<br />
employ wire-bonded source and gate interconnect.<br />
MODELING PROJECTS 49% REDUCTION IN POWER LOSS<br />
A vehicle level traction drive simulator was developed at<br />
ORNL to assess the benefits of the initial GaN on Si technology<br />
relative to an existing Silicon semiconductor based<br />
hybrid vehicle. The simulator contains motor, inverter and<br />
battery models.<br />
The motor and inverter models are generic allowing for<br />
use of design specific data. The motor model is based upon<br />
a commercial, on the road, internal permanent magnet<br />
motor, characterized by parameters extracted from benchmarking<br />
work performed at ORNL. The model allows for<br />
regenerative recovery of the vehicle’s excess kinetic energy<br />
that is conventionally wasted in the brakes by friction. The<br />
motor model takes all or part of the road-power demand<br />
as input and computes the frequency, current, voltage and<br />
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www.powerelectronics.com January 2013 | <strong>Power</strong> <strong>Electronics</strong> Technology 37<br />
Shear strength<br />
90<br />
80<br />
70<br />
60<br />
50<br />
40<br />
30<br />
20<br />
10<br />
0<br />
Low Pressure<br />
Ag Coated Substrate<br />
High Pressure<br />
0 250 500 750 1000 1250<br />
Thermal cycles (–40 °C to +135 °C)<br />
Fig. 4. Shear strength of sintered die with silver plated substrates.
PETinnovations<br />
from 0% to 100% of the required road-<br />
50<br />
power, depending on the hybridization<br />
40<br />
power-sharing scheme.<br />
30<br />
In this study, it is assumed that most<br />
20<br />
of power demand of the drive cycle<br />
will be supplied by the electric drive 10<br />
train and, in the regions where the 0<br />
demand is more than the maximum –10<br />
power of the electric motor, the engine –20<br />
will generate the power. The available –30<br />
maximum terminal voltage limits the –40<br />
output power of the motor, which is –50<br />
dependent on the dc bus voltage with<br />
maximum boost. The terminal voltage<br />
is calculated assuming six-step mode of<br />
operation of the inverter.<br />
The inverter requires the following<br />
data for a particular drive system to be simulated:<br />
(1) Number of parallel inverter legs<br />
(2) Number of diodes and switches per leg<br />
(3) Characteristic data for the diodes and switches such as:<br />
heat transfer coefficients, thermal inertias, conduction<br />
and switching loss functions with temperature, power<br />
factor and modulation index dependencies.<br />
The inverter loss model was implemented with conduction<br />
loss models developed using averaging techniques and<br />
switching loss equations derived based on general switching<br />
energy loss data. The temperature dependent conduction<br />
loss parameters, on-state resistance, voltage drops, and<br />
switching losses were obtained from actual testing of the<br />
devices at Delphi. In addition to the power, current, power<br />
factor, and voltage demands computed by the motor<br />
model, the conduction loss model requires the modulation<br />
index as input. This index was calculated as the ratio of<br />
the terminal voltage required by the motor and the dc-link<br />
2000<br />
1500<br />
1000<br />
Total <strong>Power</strong> Loss (W) 2500<br />
500<br />
0<br />
0 100 200 300<br />
Time (sec)<br />
400 500 600<br />
% Change in Rdson<br />
Fig. 6. <strong>Power</strong> Dissipation of Si vs GaN over US06 Drive Cycle.<br />
voltage provided by the boost converter.<br />
The temperature dependent power<br />
losses in the switches and diodes iterates<br />
with a thermal model that computes<br />
the junction temperatures from<br />
the power losses assuming a constant<br />
heat sink temperature.<br />
For this study, the speed and power<br />
required for the drive were generated<br />
using 2008 Toyota Camry-like<br />
reference vehicle characteristics. The<br />
driving profile followed by the vehicle<br />
was the standard US06 drive cycle; a<br />
20 minute, 8 mile long combination<br />
of urban and highway driving with<br />
80 miles per hour (mph) peak and 52<br />
mph average moving speeds. Assuming<br />
a flat terrain and no wind, the average and peak road-power<br />
demands placed on the vehicles motor were 25.1 kW/ 100<br />
kW for propulsion and 19.7 kW / 68.6 kW for braking.<br />
Fig. 6 shows the results of the system simulation, depicting<br />
the power dissipation over time for the US06 drive cycle.<br />
The simulation was performed with an inverter coolant<br />
temperature of 105°C, a dc bus voltage of 325 V, and a<br />
switching frequency of 20 kHz. The lower power losses of<br />
the GaN system are clearly evident, particularly during peak<br />
power demands.<br />
Under the stated operating conditions, the GaN on Si<br />
system realizes an increase in average efficiency over the<br />
drive cycle of over 2.8%, from 94.21% to 97.03%, which<br />
equates to a reduction in losses by 49%.<br />
Device Under Test<br />
Fig. 5. Measured change in on-state resistance after<br />
18,000 cycles at a delta-T of 100°C.<br />
600 V, 30 A Si IGBT<br />
600 600 V, 30 A GaN Cascode<br />
REFERENCES<br />
[1] “Reliability Assessment of Sintered Nano-Silver Die Attachment<br />
for <strong>Power</strong> Semiconductors”, Matthias Knoerr, Silke Kraft, Andreas<br />
Schletz, Fraunhofer Institute for Integrated Systems and Device<br />
Technology, published in the proceeding of the 2010 12th <strong>Electronics</strong><br />
Packaging Technology Conference.<br />
ACKNOWLEDGMENT:<br />
“This material is based upon work supported by the Department of<br />
Energy ARPA-E under Award Number DE-AR0000016.<br />
Disclaimer: “This report was prepared as an account of work sponsored<br />
by an agency of the United States Government. Neither the United<br />
States Government nor any agency thereof, nor any of their employees,<br />
makes any warranty, express or implied, or assumes any legal liability or<br />
responsibility for the accuracy, completeness, or usefulness of any informa-<br />
tion, apparatus, product, or process disclosed, or represents that its use<br />
would not infringe privately owned rights. Reference herein to any specific<br />
commercial product, process, or service by trade name, trademark, manu-<br />
facturer, or otherwise does not necessarily constitute or imply its endorse-<br />
ment, recommendation, or favoring by the United States Government or<br />
any agency thereof. The views and opinions of authors expressed herein<br />
do not necessarily state or reflect those of the United States Government<br />
or any agency thereof.”<br />
38 <strong>Power</strong> <strong>Electronics</strong> Technology | January 2013 www.powerelectronics.com
NEWproducts<br />
■PSB <strong>Power</strong> Shunt Allows Enhanced<br />
Absorption of Thermal Expansion<br />
DESIGNED WITH KOA Speer <strong>Electronics</strong>’ original terminal<br />
shell, the PSB allows for enhanced absorption of thermal<br />
expansion. The PSB current sensing power shunt offers a high<br />
power rating of 6W, low resistances of 0.75mΩ and 1mΩ and<br />
a tolerance of 1%.<br />
Due to its special 0.2mm-thick Cu electrode shape, KOA<br />
Speer’s PSB resistor features excellent temperature cycling<br />
characteristics. At the low height of 0.65mm, it is a flat structure<br />
with a TCR of ±75ppm, and is applicable for strong mounting<br />
as well as automatic mounting machines. The robust PSB<br />
features a higher resistance to solder cracking and a smooth<br />
current flow ideal for large current detecting.<br />
The PSB is ideal for use in current sensing automotive and<br />
industrial applications for ECUs, such as electronic controls, EV<br />
and HEV battery management, DC/DC converters, oil and gas<br />
down hole equipment, air conditioning/heat pumping, inverter<br />
controls, electronic power steering, electric brake systems and<br />
water/oil pumps. Prices start at $3.50 each.<br />
■Super Dielectric Option for High-Voltage<br />
MLC Radial Leaded Capacitors<br />
AVX CORPORATION has added an N1500 super dielectric option to<br />
its high-voltage, multilayer ceramic (MLC), radial leaded capacitor<br />
series. An extension of the SV Series, the new N1500 super dielectric<br />
capacitors take up less board space and offer higher capacitance values<br />
than comparable C0G dielectric capacitors and are ideally suited<br />
for applications including snubbers in high-frequency power converters,<br />
resonators in SMPS, AC<br />
line filtering, and high-voltage<br />
coupling/DC blocking.<br />
AVX’s high-voltage SV Series<br />
MLC radial leaded capacitors<br />
are coated with high insulation<br />
resistance and high dielectric<br />
strength epoxy, which eliminates<br />
the possibility of arc flashover. The series also exhibits low<br />
ESRs at high frequencies.<br />
The new N1500 dielectric SV Series capacitors feature a capacitance<br />
range of 100pF to 0.47µF with tolerances of ±5%, ±10%,<br />
and 20%, a voltage range of 600-5000V, and a maximum dissipation<br />
factor of 0.15%. The operating temperature range for the series<br />
is -55°C to +125°C. Additionally, a Hi-Rel screening option (100%<br />
Group A testing per MIL-PRF-49467) is available.<br />
All parts are priced upon request, and lead time is 11-14 weeks.<br />
AVX<br />
KOA Speer <strong>Electronics</strong>, Inc.<br />
Bradford, PA<br />
http://www.KOASpeer.com<br />
Greenville, SC<br />
http://www.avx.com<br />
■Flexible Wire for <strong>Power</strong> Distribution Applications<br />
TE CONNECTIVITY (TE) has introduced the SHF-260 highly flexible<br />
wire for power distribution applications within the aerospace,<br />
defense and marine markets. The highly flexible cable can be<br />
bent and routed in extremely tight areas. As a result, SHF-260<br />
flexible wire is able to run shorter distances, reducing the stress<br />
on the contact, and reducing<br />
the mating and demating forces<br />
normally associated with large<br />
shell diameter circular connectors,<br />
such as MIL-DTL-5015 and<br />
MIL-DTL-83723 connectors.<br />
The SHF-260 flexible wire is<br />
made with extruded polymer,<br />
making it more notch and abrasion resistant as well as mechanically<br />
tough. It is available in 0 to 24 AWG size, with a nominal voltage<br />
rating of 1000 Volts. Insulation resistance is 50,000 Mohms/kft,<br />
and insulation elongation is 150 percent minimum.<br />
TE Connectivity<br />
Harrisburg, PA<br />
http://www.te.com<br />
CURRENT SENSE<br />
RESISTORS<br />
RoHS COMPLIANT<br />
■ Small, compact design<br />
■ Very low ohmic values<br />
(beginning at 0.5mR)<br />
■ 4-terminal Kelvin<br />
connection<br />
■ Non-inductive<br />
■ Resistance tolerances:<br />
1%, 2%, 5%<br />
MODEL POWER<br />
NUMBER RATING<br />
PCS-3 Pulse current<br />
3W@70°C up to 200 Amps<br />
for .5 seconds,<br />
depending on<br />
value<br />
PCS-100 Pulse current<br />
100W@70°C up to 500 Amps<br />
for .5 seconds,<br />
depending on<br />
value<br />
EBG RESISTORS LLC<br />
Middletown, PA 17057<br />
Phone (717) 737-9877<br />
Fax (717) 737-9664<br />
www.ebgusa.com<br />
PRECISION YOU CAN COUNT ON!<br />
www.powerelectronics.com January 2013 | <strong>Power</strong> <strong>Electronics</strong> Technology 39
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A A Supplement Special Section to Microwaves to Penton’s Design & RF • Electronic Engineering Design & Sourcing • <strong>Power</strong> Group <strong>Electronics</strong> Technology OCTOBER/NOVEMBER MARCH/APRIL 2010 2012<br />
Electronic<br />
Passengers<br />
ADVERTISERindex<br />
16 | COTS GEAR FOR MILITARY TESTING 21 | MATERIALS FOR MILITARY CIRCUITS<br />
WHERE ENGINEERING COMES FIRST<br />
Advanced <strong>Power</strong> <strong>Electronics</strong> Corp. USA ............................... 21<br />
Ametherm ........................................................................... 25<br />
APEC 2013 ......................................................................... 15<br />
Avnet Embedded ................................................................ IBC<br />
Coilcraft ............................................................................. BC<br />
EBG Resistors LCC ............................................................... 39<br />
International Rectifi er ......................................................... IFC<br />
IXYS .................................................................................... 26<br />
IXYS Colorado ..................................................................... 37<br />
Linear Technology Corporation .............................................. 1<br />
Mean Well USA ..................................................................... 5<br />
Mouser <strong>Electronics</strong> .........................................................7, 11<br />
Payton America ................................................................... 19<br />
Trim-Lok ............................................................................. 13<br />
This Advertiser Index is printed as a courtesy only.<br />
<strong>Power</strong> <strong>Electronics</strong> Technology is not responsible for errors or omissions.<br />
40 <strong>Power</strong> <strong>Electronics</strong> Technology | January 2013 www.powerelectronics.com<br />
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