DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...

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Error, CRC Error, Acknowledge Error, and Stuff Error. A summary of these error checking methods is provided in Table 3.3. Bit ErrorEvery transmitting node monitors its own messages as it transmits them across the bus, checking the bits in each frame for errors. A transmitting node always reads back the message as it is sending [21 – 22]. The node will detect a Bit Error if it sends out a dominant bit when it was supposed to transmit a recessive bit, or a recessive bit when the message called for a dominant bit. Also, if the bit is not part of the Arbitration Field or Acknowledge Slot, a Bit Error has been detected. At this point, an Error Frame is generated and the original message is then resent after a proper intermission time. Form ErrorThe first bit in every frame must always be a dominant bit. If any node in the network detects a dominant bit in one of the following four segments of the message: End-Of-Frame, Interframe Space, Acknowledge Delimiter, or CRC Delimiter, a Form Error has occurred. An Error Frame is then generated and the original message is then resent later after a proper intermission time. CRC ErrorCyclic redundancy checking is a very effective method of looking for errors in a network by applying a polynomial equation to a block of transmitted data. The transmitting node calculates a 15-bit CRC value according to the polynomial Gxin Equation 3.1. The CAN bus applies a CRC-15 with a hamming distance of D 6 for 8 byte information data packets. All nodes on the network receive this message, calculate their own CRC and verify that the CRC values match. If the values do not match, a CRC 59
error occurs, an Error Frame is generated by the receiving node, and the message is then resent later after a proper intermission time. 15 14 10 8 7 4 3 G x x x x x x x x 1 (3.1) Acknowledge ErrorIn the ACK bit field of a message, the transmitting node checks if the ACK bit slot, which is sent as a ‘recessive’ bit, contains a ‘dominant’ bit. A ‘dominant’ bit implies at least one node correctly received the message. A ‘recessive’ bit means no node received the message and an ACK Error occurs. An Error Frame is generated by the original transmitting node, and the original message is then resent later after a proper intermission time. Stuff ErrorReceiving nodes check for a violation of the bit stuffing rule. The final method of error detection uses the bit stuffing rule where after five consecutive bits of the same logic level, if the next bit is not a complement, an error is generated. Bit stuffing by the transmitter ensures that rising edges are available for on-going synchronization of the network. Bit stuffing also ensures that a stream of bits is not mistaken for an error frame or the seven-bit interframe space that signifies the end of a message. Stuffed bits are removed by a receiving node’s controller before the data is forwarded to the application. If there are more than five bits of the same polarity in a row, a bit of the opposite polarity is automatically stuffed into the data stream. This will be used by the receiving nodes for synchronization, but ignored for data purposes. If between the Start-Of-Frame and the CRC Delimiter, six consecutive bits with the same polarity are detected, a Stuff Error has occurred. An Error Frame is then generated by the receiving node, and the original message is then resent later after a proper intermission time. 60
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DESIGN OF A CUSTOM ASIC INCORPORATI
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ABSTRACT The vast majority of today
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LIST OF ABBREVIATIONS AND SYMBOLS A
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ISO International Organization for
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SI Serial In SO Serial Out SOF Star
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ACKNOWLEDGEMENTS I would like to ex
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2.4 Types of Devices...............
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4.3.5 Communication Speed Different
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5.3.21.1 Synchronization Test (test
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5.3 Resource Utilization...........
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LIST OF FIGURES 2.1 1 - Wire® Netw
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4.12 Read-Data Time Slot...........
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6.4 DS1996 Address Registers ......
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manufacturing process. Structured o
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describes the 1 - Wire® and CAN co
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2.2 1 - Wire® Overview The basis o
Page 33 and 34: All 1 - Wire® masters described in
Page 35 and 36: attachments, microcontroller with b
Page 37 and 38: Figure 2.3 Bidirectional port pin w
Page 39 and 40: 2.3.3 Synthesizable 1 - Wire® Bus
Page 41 and 42: Figure 2.7 UART/RS232 Serial Port I
Page 43 and 44: hardware. Through control registers
Page 45 and 46: Table 2.2 1 - Wire® Bus Operations
Page 47 and 48: 2.3.6 1 - Wire® Search Algorithm F
Page 49 and 50: detected. This ‘read two bits’
Page 51 and 52: in Figure 2.15. Alternatively, the
Page 53 and 54: of the bit, then write the desired
Page 55 and 56: 2.4.2 Device Functions and Typical
Page 57 and 58: and development (R&D) investments b
Page 59 and 60: 2.5 Network Types and Precedents As
Page 61 and 62: 2.5.2 1 - Wire® Network Topologies
Page 63 and 64: 2.5.3 1 - Wire® Network Limitation
Page 65 and 66: with a single selected slave. If an
Page 67 and 68: user group was founded in March of
Page 69 and 70: protocol on multiple media for maxi
Page 71 and 72: ecessive bit and the monitored stat
Page 73 and 74: specification: Start-Of-Frame, Arbi
Page 75 and 76: Cyclic Redundancy Check (CRC) Field
Page 77 and 78: Arbitration FieldThe Arbitration Fi
Page 79 and 80: SOF SOF Bit 28 Bit 27 Arbitration f
Page 81 and 82: Afterwards it starts transmitting s
Page 83: Figure 3.9 Structure of the Interfr
Page 87 and 88: Table 3.4 Error Flag Output Timing
Page 89 and 90: 3.5.2 Error-Passive A node becomes
Page 91 and 92: where tNBT is the Nominal Bit Time
Page 93 and 94: Figure 3.12 Propagation Delay Betwe
Page 95 and 96: 3.6.4 Synchronization t t t t (3.
Page 97 and 98: opposite value is inserted into the
Page 99 and 100: many systems, the bus length will b
Page 101 and 102: CHAPTER 4 THE CHALLENGES OF INTERFA
Page 103 and 104: In June 2004, Maxim Integrated Prod
Page 105 and 106: Wearable sensor technology is a new
Page 107 and 108: In traditional bus architectures, o
Page 109 and 110: Figure 4.3 Centralized arbiter with
Page 111 and 112: For the initial prototype design pr
Page 113 and 114: the ID of 31 transmits a ‘0’ (d
Page 115 and 116: Recently, a technique has been prop
Page 117 and 118: procedure, then the address claim p
Page 119 and 120: paradigms are prevalent in the desi
Page 121 and 122: systems possess a higher flexibilit
Page 123 and 124: fixed identifier and hence a fixed
Page 125 and 126: 348sm Cm 47 8 smbit 11-bit hea
Page 127 and 128: est-case latency occurs when the bu
Page 129 and 130: to break the 1 - Wire® network int
Page 131 and 132: ow, is most critical for power deli
Page 133 and 134: computations have device-specific p
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Table 4.7 Example results with N 2
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4.3.5 Communication Speed Different
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anging” a port pin on a microproc
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From Figure 5.1, the block I/O pins
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5.2.2 Command Register In addition
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specifies the selected bit value to
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with i > m. This process is repeate
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Figure 5.6 Interrupt Register. OW_
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the INTR pin will be pulled high si
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master reset occurs. Table 5.2 show
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EN_FOW: Enable Force One Wire. Sett
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READ_ROM - Used to read the 64-bit
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5.2.8.1 Single Search ROM (single_s
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5.2.8.3 Scratchpad Memory (scratchp
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5.2.8.4 Command Recognition (cmd_re
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TBF - The Transmit Buffer provides
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compensate for the propagation dela
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Figure 5.15 CAN Module memory map [
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‘0’, fast speed mode will be us
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COMP-SEL: Comparator Select. When t
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Figure 5.18 CAN Status Register. B
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that buffer is given to the CPU and
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Acceptance Mask Registers (accepted
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SJW1, SJW0: Synchronization Jump Wi
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TSEG22 - TSEG10: Time Segment Bits.
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The transmit clock (ttxclk) is used
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5.3.13 CAN Module Transmit Buffer I
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Figure 5.28 CAN Transmit Data Segme
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5.3.20 CAN Node Overview As stated
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Read Digital InputsRead the value o
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the clock high time is either 5 µs
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Yes Perform A/D Conversion on AN0 W
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and GP2 and GP5 as outputs. With th
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external INT pin, and then branches
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Read MCP2515 Rx Buffer for Digital
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When a valid message is received, t
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Table 5.19 Resource Utilization. Re
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For this test, only one CAN node wa
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an Error Frame to be generated. Aft
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messages, acknowledge messages, or
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5.3.21.4 Send Basic Frame Test (sen
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going from one node to 30 nodes (se
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Table 6.1 Resource Utilization. Rev
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6.2.1 Test Verification and Overvie
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has read access to this register. T
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system configuration used for this
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or not depends on the number of rec
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6.4. There are two receiving CAN no
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CHAPTER 7 CONCLUSIONS AND FUTURE WO
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a communication bus reset will occu
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For the synthesizable CAN Controlle
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additional CAN nodes were added to
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Fall-Through Stack A LOW level on t
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In conclusion, the prototype system
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REFERENCES [1] IBM ASIC Products Ap
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[22] “CAN - a brief tutorial for
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[44] Microchip MCP2515 - Stand-Alon
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[67] K. Tindell and A. Burns, “Gu
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[88] “Verilog - A Language Refere
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