DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...
DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ... DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...
From Figure 2.15, the input data gets exclusive-or’d with the output of the eighth stage of the shift register. The shift register can be considered mathematically as a dividing circuit. The input data is the dividend, and the shift register with feedback acts as a divisor. The resulting quotient is discarded, and the remainder is the CRC value for that particular stream of input data, which resides in the shift register after the last data bit has been shifted in. The final result (CRC value) is dependent on the past history of the bits presented. Therefore, it would take an extremely rare combination of errors to escape detection by this method [17]. 2.3.8 1 – Wire® Commands After initialization has been completed and the bus master has detected a presence pulse on the bus, it can issue one of the following ROM function commands: READ ROM [33h] – This command allows the bus master to read a device’s 8 – bit family code, unique 48 – bit serial number, and 8 – bit CRC code. This command can only be used if there is a single slave device on the bus. If more than one slave (See Figure 2.1) is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired – AND result). The resultant family code and 48 – bit serial number will result in a mismatch of the CRC. SEARCH ROM [F0h] – When a system is initialized, the bus master might not know the number of devices on the 1 – Wire® bus or their registration numbers. The SEARCH ROM command allows the bus master to use a process of elimination to identify the 64 – bit ROM codes of all slave devices on the bus. The process is the repetition of a simple 3 – step routine on each bit of the ROM by the bus master: read a bit, read the complement 27
of the bit, then write the desired value of that bit. After one complete pass, the bus master knows the contents of the ROM in one device. The remaining number of devices and their ROM codes can be identified by additional passes. MATCH ROM [55h] – This command followed by a 64 – bit ROM sequence, allows the bus master to address a specific slave device on a bus topology having one or more slaves. Only the device that exactly matches the 64 – bit ROM sequence will respond to the following memory function command. All slaves that do not match the 64 – bit ROM sequence wait for a reset pulse. SKIP ROM [CCh] – This command can save time in a single slave network by allowing the bus master to access the memory functions without providing the 64 – bit ROM code. If more than one slave is present on the bus and, for example, a read command is issued following the SKIP ROM command, data collision will occur on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wired – AND result). All iButtons and 1 – Wire® devices support at least some basic set of ROM function commands such as those previously mentioned. The number of supported ROM functions depends on the device itself but most importantly, these ROM functions (there are a total of 9) have the same command number regardless of the iButton or 1 – Wire® device being used. After a ROM function command has been successfully executed, the bus master may then provide any one of the memory function commands specific to the device being addressed. (See device documentation for specific number and type of memory functions as these can be different for each device and also not all devices support these commands.) This allows further data and other transactions to take place between the bus master and slave devices. 28
- Page 1 and 2: DESIGN OF A CUSTOM ASIC INCORPORATI
- Page 3 and 4: ABSTRACT The vast majority of today
- Page 5 and 6: LIST OF ABBREVIATIONS AND SYMBOLS A
- Page 7 and 8: ISO International Organization for
- Page 9 and 10: SI Serial In SO Serial Out SOF Star
- Page 11 and 12: ACKNOWLEDGEMENTS I would like to ex
- Page 13 and 14: 2.4 Types of Devices...............
- Page 15 and 16: 4.3.5 Communication Speed Different
- Page 17 and 18: 5.3.21.1 Synchronization Test (test
- Page 19 and 20: 5.3 Resource Utilization...........
- Page 21 and 22: LIST OF FIGURES 2.1 1 - Wire® Netw
- Page 23 and 24: 4.12 Read-Data Time Slot...........
- Page 25 and 26: 6.4 DS1996 Address Registers ......
- Page 27 and 28: manufacturing process. Structured o
- Page 29 and 30: describes the 1 - Wire® and CAN co
- Page 31 and 32: 2.2 1 - Wire® Overview The basis o
- Page 33 and 34: All 1 - Wire® masters described in
- Page 35 and 36: attachments, microcontroller with b
- Page 37 and 38: Figure 2.3 Bidirectional port pin w
- Page 39 and 40: 2.3.3 Synthesizable 1 - Wire® Bus
- Page 41 and 42: Figure 2.7 UART/RS232 Serial Port I
- Page 43 and 44: hardware. Through control registers
- Page 45 and 46: Table 2.2 1 - Wire® Bus Operations
- Page 47 and 48: 2.3.6 1 - Wire® Search Algorithm F
- Page 49 and 50: detected. This ‘read two bits’
- Page 51: in Figure 2.15. Alternatively, the
- Page 55 and 56: 2.4.2 Device Functions and Typical
- Page 57 and 58: and development (R&D) investments b
- Page 59 and 60: 2.5 Network Types and Precedents As
- Page 61 and 62: 2.5.2 1 - Wire® Network Topologies
- Page 63 and 64: 2.5.3 1 - Wire® Network Limitation
- Page 65 and 66: with a single selected slave. If an
- Page 67 and 68: user group was founded in March of
- Page 69 and 70: protocol on multiple media for maxi
- Page 71 and 72: ecessive bit and the monitored stat
- Page 73 and 74: specification: Start-Of-Frame, Arbi
- Page 75 and 76: Cyclic Redundancy Check (CRC) Field
- Page 77 and 78: Arbitration FieldThe Arbitration Fi
- Page 79 and 80: SOF SOF Bit 28 Bit 27 Arbitration f
- Page 81 and 82: Afterwards it starts transmitting s
- Page 83 and 84: Figure 3.9 Structure of the Interfr
- Page 85 and 86: error occurs, an Error Frame is gen
- Page 87 and 88: Table 3.4 Error Flag Output Timing
- Page 89 and 90: 3.5.2 Error-Passive A node becomes
- Page 91 and 92: where tNBT is the Nominal Bit Time
- Page 93 and 94: Figure 3.12 Propagation Delay Betwe
- Page 95 and 96: 3.6.4 Synchronization t t t t (3.
- Page 97 and 98: opposite value is inserted into the
- Page 99 and 100: many systems, the bus length will b
- Page 101 and 102: CHAPTER 4 THE CHALLENGES OF INTERFA
From Figure 2.15, the input data gets exclusive-or’d with the output of the eighth stage of the<br />
shift register. The shift register can be considered mathematically as a dividing circuit. The<br />
input data is the dividend, and the shift register with feedback acts as a divisor. The resulting<br />
quotient is discarded, and the remainder is the CRC value for that particular stream of input data,<br />
which resides in the shift register after the last data bit has been shifted in. The final result (CRC<br />
value) is dependent on the past history of the bits presented. Therefore, it would take an<br />
extremely rare combination of errors to escape detection by this method [17].<br />
2.3.8 1 – Wire® Commands<br />
After initialization has been completed and the bus master has detected a presence pulse<br />
on the bus, it can issue one of the following ROM function commands:<br />
READ ROM [33h] – This command allows the bus master to read a device’s 8 – bit<br />
family code, unique 48 – bit serial number, and 8 – bit CRC code. This command can<br />
only be used if there is a single slave device on the bus. If more than one slave (See<br />
Figure 2.1) is present on the bus, a data collision will occur when all slaves try to transmit<br />
at the same time (open drain will produce a wired – <strong>AND</strong> result). The resultant family<br />
code and 48 – bit serial number will result in a mismatch of the CRC.<br />
SEARCH ROM [F0h] – When a system is initialized, the bus master might not know the<br />
number of devices on the 1 – Wire® bus or their registration numbers. The SEARCH<br />
ROM command allows the bus master to use a process of elimination to identify the 64 –<br />
bit ROM codes of all slave devices on the bus. The process is the repetition of a simple 3<br />
– step routine on each bit of the ROM by the bus master: read a bit, read the complement<br />
27
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