DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...
DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ... DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...
Figure 2.8 I 2 C interface with optional circuit for extra strong pullup (dashed lines) [8]. Figure 2.9 1 – Wire® Master for a USB interface [8]. A 1 – Wire® Master application circuit can also be created using a USB port, as shown in Figure 2.9. The upside of this implementation is that the 1 – Wire® timing is generated by 17
hardware. Through control registers, the 1 – Wire® timing can be fine-tuned. The DS2490, like the DS2482 and DS2480B, supports a strong pullup and an active pullup. On the downside, the DS2490 is more costly than the other implementations presented here and also the DS2490 pullup is not as strong as the DS2480B. In addition to the interface circuits described previously, 1 – Wire® can also be connected to a PC using a bus converter. The primary function of the bus converter is to generate the appropriate 1 – Wire® communication signals and perform level conversion depending on the type of port device used. USB, RS232 serial, and parallel port adapters are available to connect 1 – Wire® devices to a host PC. Table 2.1 lists the different types of PC adapters available. Since the PC-ready adapters do not require any software development by the user, PC attachments that function as a 1 – Wire® Master are very convenient for evaluating 1 – Wire® devices and for prototyping. Table 2.1 Port Adapters for 1 – Wire® Devices. Port Type Converter 1 – Wire® Port Part Number Notes USB DS2490 iButton RJ – 11 DS9490B DS9490R Built-in ID chip is hardwired to 1 – Wire® bus iButton DS1411-009 Built-in ID chip is hardwired to 1 – Wire® bus DS1411-S09 No ID chip RS232 DS2480B DS9097U-009 Built-in IC chip is hardwired to 1 – Wire® bus RJ – 11 DS9097U-S09 No ID chip No ID chip; w/ external 12V supply, DS9097U-E25 this adapter can program 1 – Wire® EPROMs Parallel DS1481 iButton DS1410E-001 Built-in ID chip is hardwired to 1 – Wire® bus 18
- Page 1 and 2: DESIGN OF A CUSTOM ASIC INCORPORATI
- Page 3 and 4: ABSTRACT The vast majority of today
- Page 5 and 6: LIST OF ABBREVIATIONS AND SYMBOLS A
- Page 7 and 8: ISO International Organization for
- Page 9 and 10: SI Serial In SO Serial Out SOF Star
- Page 11 and 12: ACKNOWLEDGEMENTS I would like to ex
- Page 13 and 14: 2.4 Types of Devices...............
- Page 15 and 16: 4.3.5 Communication Speed Different
- Page 17 and 18: 5.3.21.1 Synchronization Test (test
- Page 19 and 20: 5.3 Resource Utilization...........
- Page 21 and 22: LIST OF FIGURES 2.1 1 - Wire® Netw
- Page 23 and 24: 4.12 Read-Data Time Slot...........
- Page 25 and 26: 6.4 DS1996 Address Registers ......
- Page 27 and 28: manufacturing process. Structured o
- Page 29 and 30: describes the 1 - Wire® and CAN co
- Page 31 and 32: 2.2 1 - Wire® Overview The basis o
- Page 33 and 34: All 1 - Wire® masters described in
- Page 35 and 36: attachments, microcontroller with b
- Page 37 and 38: Figure 2.3 Bidirectional port pin w
- Page 39 and 40: 2.3.3 Synthesizable 1 - Wire® Bus
- Page 41: Figure 2.7 UART/RS232 Serial Port I
- Page 45 and 46: Table 2.2 1 - Wire® Bus Operations
- Page 47 and 48: 2.3.6 1 - Wire® Search Algorithm F
- Page 49 and 50: detected. This ‘read two bits’
- Page 51 and 52: in Figure 2.15. Alternatively, the
- Page 53 and 54: of the bit, then write the desired
- Page 55 and 56: 2.4.2 Device Functions and Typical
- Page 57 and 58: and development (R&D) investments b
- Page 59 and 60: 2.5 Network Types and Precedents As
- Page 61 and 62: 2.5.2 1 - Wire® Network Topologies
- Page 63 and 64: 2.5.3 1 - Wire® Network Limitation
- Page 65 and 66: with a single selected slave. If an
- Page 67 and 68: user group was founded in March of
- Page 69 and 70: protocol on multiple media for maxi
- Page 71 and 72: ecessive bit and the monitored stat
- Page 73 and 74: specification: Start-Of-Frame, Arbi
- Page 75 and 76: Cyclic Redundancy Check (CRC) Field
- Page 77 and 78: Arbitration FieldThe Arbitration Fi
- Page 79 and 80: SOF SOF Bit 28 Bit 27 Arbitration f
- Page 81 and 82: Afterwards it starts transmitting s
- Page 83 and 84: Figure 3.9 Structure of the Interfr
- Page 85 and 86: error occurs, an Error Frame is gen
- Page 87 and 88: Table 3.4 Error Flag Output Timing
- Page 89 and 90: 3.5.2 Error-Passive A node becomes
- Page 91 and 92: where tNBT is the Nominal Bit Time
Figure 2.8 I 2 C interface with optional circuit for extra strong pullup (dashed lines) [8].<br />
Figure 2.9 1 – Wire® Master for a USB interface [8].<br />
A 1 – Wire® Master application circuit can also be created using a USB port, as shown in<br />
Figure 2.9. The upside of this implementation is that the 1 – Wire® timing is generated by<br />
17
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