DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...
DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ... DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...
2.3.4 Serial Interface Protocol Conversions The final category of 1 – Wire® Master implementation is created using an interface between some type of controller and an off-the-shelf 1 – Wire® Master. As shown in Figure 2.7, one way to accomplish this is to interface the controller to the 1 – Wire® Master via a serial interface. This implementation requires a way to control a UART, such as a microcontroller, FPGA, or PC serial port, and some spare space in the program memory. The upside of this design is that the 1 – Wire® timing is generated by hardware leading to the benefits mentioned above. Through control registers, the 1 – Wire® timing can be fine-tuned. The DS2480B is a serial port to 1 – Wire® interface chip that supports both standard and overdrive speeds [12]. It directly interfaces UARTs and 5V RS232 systems with its lines TXD (transmit) and RXD (receive) to a 1 – Wire® bus. In addition, the device performs a speed conversion allowing the data rate at the communication port to be different from the 1 – Wire® data rate. The DS2480B supports a strong pullup and active pullup. It is also the strongest (i.e. capable of delivering the most power) single-chip 1 – Wire® Master available and is good for communicating with a large number of slave devices. On the downside, the DS2480B is more costly than the discrete components shown in Figures 2.3 through 2.6. 15
Figure 2.7 UART/RS232 Serial Port Interface [8]. For those applications that already use an I 2 C [9] bus, the implementation in Figure 2.8 is most convenient to establish a 1 – Wire® Master. This design makes use of an existing I 2 C bus controller, such as a microcontroller, or ASIC/FPGA, and some spare space in the program memory. The advantages to this implementation are its relatively low cost for the features provided, and the fact that the 1 – Wire® timing is generated by hardware. The DS2482 supports a strong pullup as well as an active pullup. On the downside, the DS2482 cannot drive as many 1 – Wire® slave devices as the DS2490 or DS2480B. The single-channel version, the DS2482-100 as shown in Figure 2.8, has a control output for an additional strong pullup (Q1) circuit as shown in Figures 2.3 through 2.6 [13 – 15]. 16
- Page 1 and 2: DESIGN OF A CUSTOM ASIC INCORPORATI
- Page 3 and 4: ABSTRACT The vast majority of today
- Page 5 and 6: LIST OF ABBREVIATIONS AND SYMBOLS A
- Page 7 and 8: ISO International Organization for
- Page 9 and 10: SI Serial In SO Serial Out SOF Star
- Page 11 and 12: ACKNOWLEDGEMENTS I would like to ex
- Page 13 and 14: 2.4 Types of Devices...............
- Page 15 and 16: 4.3.5 Communication Speed Different
- Page 17 and 18: 5.3.21.1 Synchronization Test (test
- Page 19 and 20: 5.3 Resource Utilization...........
- Page 21 and 22: LIST OF FIGURES 2.1 1 - Wire® Netw
- Page 23 and 24: 4.12 Read-Data Time Slot...........
- Page 25 and 26: 6.4 DS1996 Address Registers ......
- Page 27 and 28: manufacturing process. Structured o
- Page 29 and 30: describes the 1 - Wire® and CAN co
- Page 31 and 32: 2.2 1 - Wire® Overview The basis o
- Page 33 and 34: All 1 - Wire® masters described in
- Page 35 and 36: attachments, microcontroller with b
- Page 37 and 38: Figure 2.3 Bidirectional port pin w
- Page 39: 2.3.3 Synthesizable 1 - Wire® Bus
- Page 43 and 44: hardware. Through control registers
- Page 45 and 46: Table 2.2 1 - Wire® Bus Operations
- Page 47 and 48: 2.3.6 1 - Wire® Search Algorithm F
- Page 49 and 50: detected. This ‘read two bits’
- Page 51 and 52: in Figure 2.15. Alternatively, the
- Page 53 and 54: of the bit, then write the desired
- Page 55 and 56: 2.4.2 Device Functions and Typical
- Page 57 and 58: and development (R&D) investments b
- Page 59 and 60: 2.5 Network Types and Precedents As
- Page 61 and 62: 2.5.2 1 - Wire® Network Topologies
- Page 63 and 64: 2.5.3 1 - Wire® Network Limitation
- Page 65 and 66: with a single selected slave. If an
- Page 67 and 68: user group was founded in March of
- Page 69 and 70: protocol on multiple media for maxi
- Page 71 and 72: ecessive bit and the monitored stat
- Page 73 and 74: specification: Start-Of-Frame, Arbi
- Page 75 and 76: Cyclic Redundancy Check (CRC) Field
- Page 77 and 78: Arbitration FieldThe Arbitration Fi
- Page 79 and 80: SOF SOF Bit 28 Bit 27 Arbitration f
- Page 81 and 82: Afterwards it starts transmitting s
- Page 83 and 84: Figure 3.9 Structure of the Interfr
- Page 85 and 86: error occurs, an Error Frame is gen
- Page 87 and 88: Table 3.4 Error Flag Output Timing
- Page 89 and 90: 3.5.2 Error-Passive A node becomes
2.3.4 Serial Interface Protocol Conversions<br />
The final category of 1 – Wire® Master implementation is created using an interface<br />
between some type of controller and an off-the-shelf 1 – Wire® Master. As shown in Figure 2.7,<br />
one way to accomplish this is to interface the controller to the 1 – Wire® Master via a serial<br />
interface. This implementation requires a way to control a UART, such as a microcontroller,<br />
FPGA, or PC serial port, and some spare space in the program memory. The upside of this<br />
design is that the 1 – Wire® timing is generated by hardware leading to the benefits mentioned<br />
above. Through control registers, the 1 – Wire® timing can be fine-tuned.<br />
The DS2480B is a serial port to 1 – Wire® interface chip that supports both standard and<br />
overdrive speeds [12]. It directly interfaces UARTs and 5V RS232 systems with its lines TXD<br />
(transmit) and RXD (receive) to a 1 – Wire® bus. In addition, the device performs a speed<br />
conversion allowing the data rate at the communication port to be different from the 1 – Wire®<br />
data rate. The DS2480B supports a strong pullup and active pullup. It is also the strongest (i.e.<br />
capable of delivering the most power) single-chip 1 – Wire® Master available and is good for<br />
communicating with a large number of slave devices. On the downside, the DS2480B is more<br />
costly than the discrete components shown in Figures 2.3 through 2.6.<br />
15
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