DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...

2.3.1 Microprocessor Port-Pin Attachments
As the only prerequisite, this configuration requires a microprocessor with a spare
bidirectional port pin and some spare space in the program memory. Figure 2.3 shows the most
basic implementation of this 1 – Wire® Master. The upside of this implementation is its low,
additional hardware cost, since it requires just a pullup resistor. On the downside, the 1 – Wire®
timing, to communicate with slave devices, is generated through software, which can increase
the initial software development time and cost. Depending on the number of 1 – Wire® slaves
on the bus and the 1 – Wire® pullup voltage, an additional port pin may be required to
implement a strong pullup. With more than one slave device on the 1 – Wire® bus, the value of
RPUP needs to be lowered. If communicating with 1 – Wire® slaves at overdrive speed, a
microcontroller with a high clock frequency and/or a low number of clock cycles per instruction
is required.
A variation of the implementation shown in Figure 2.3 is shown in Figure 2.4. As a
prerequisite, this new implementation requires two spare unidirectional port pins, a pulldown
transistor, and some spare space in the program memory. The upside of this design is that it does
not need a bidirectional port pin, but on the downside, the 1 – Wire® timing is generated through
software, which can increase the initial software development time and cost. Depending on the
number of 1 – Wire® slaves on the bus and the 1 – Wire® pullup voltage, an additional port pin
may be required to implement a strong pullup. With more than one slave device on the 1 –
Wire® bus, the value of RPUP needs to be lowered. If communicating with 1 – Wire® slaves at
overdrive speed, a microcontroller with a high clock frequency and/or a low number of clock
cycles per instruction is required.
11