DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...
DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ... DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...
5.22 CAN Bus Timing Register 0 ..................................................................................................155 5.23 CAN Module Oscillator Block Diagram ...............................................................................157 5.24 CAN Bus Timing Register 1 ..................................................................................................157 5.25 CAN Output Control Register ...............................................................................................159 5.26 CAN Transmit Buffer Identifier Register ..............................................................................162 5.27 CAN Remote Transmission Request/Data Length Code Register ........................................162 5.28 CAN Transmit Data Segment Registers ................................................................................164 5.29 CAN Receive Buffer Identifier Register ................................................................................165 5.30 CAN Remote Transmission Request/Data Length Code Register ........................................165 5.31 CAN Receive Data Segment Registers ..................................................................................165 5.32 CAN Node Block Diagram ....................................................................................................167 5.33 CAN Node Operation Flowchart ...........................................................................................172 5.34 PIC12CE674 Pin Names ............................................................................................................173 5.35 CAN Node Interrupt Service Routine Flowchart ...................................................................176 5.36 Timer0 Interrupt Service Routine Flowchart .............................................................................177 5.37 CAN Node Message Received Flowchart .............................................................................178 5.38 Error Handler Routine Flowchart ..............................................................................................179 5.39 Bus-Off Test Setup ....................................................................................................................184 5.40 Error Test Setup .........................................................................................................................188 6.1 Combined CAN & 1 – Wire® Prototype System ....................................................................193 6.2 1 – Wire® & CAN Combined Prototype System ....................................................................195 6.3 DS1996 iButton Memory Map ................................................................................................197 xxiii
6.4 DS1996 Address Registers ..........................................................................................................198 6.5 RXB1CTRL – Receive Buffer 1 Control Register Bit Definitions .............................................202 7.1 FIFO Buffer Memory ...................................................................................................................213 xxiv
- Page 1 and 2: DESIGN OF A CUSTOM ASIC INCORPORATI
- Page 3 and 4: ABSTRACT The vast majority of today
- Page 5 and 6: LIST OF ABBREVIATIONS AND SYMBOLS A
- Page 7 and 8: ISO International Organization for
- Page 9 and 10: SI Serial In SO Serial Out SOF Star
- Page 11 and 12: ACKNOWLEDGEMENTS I would like to ex
- Page 13 and 14: 2.4 Types of Devices...............
- Page 15 and 16: 4.3.5 Communication Speed Different
- Page 17 and 18: 5.3.21.1 Synchronization Test (test
- Page 19 and 20: 5.3 Resource Utilization...........
- Page 21 and 22: LIST OF FIGURES 2.1 1 - Wire® Netw
- Page 23: 4.12 Read-Data Time Slot...........
- Page 27 and 28: manufacturing process. Structured o
- Page 29 and 30: describes the 1 - Wire® and CAN co
- Page 31 and 32: 2.2 1 - Wire® Overview The basis o
- Page 33 and 34: All 1 - Wire® masters described in
- Page 35 and 36: attachments, microcontroller with b
- Page 37 and 38: Figure 2.3 Bidirectional port pin w
- Page 39 and 40: 2.3.3 Synthesizable 1 - Wire® Bus
- Page 41 and 42: Figure 2.7 UART/RS232 Serial Port I
- Page 43 and 44: hardware. Through control registers
- Page 45 and 46: Table 2.2 1 - Wire® Bus Operations
- Page 47 and 48: 2.3.6 1 - Wire® Search Algorithm F
- Page 49 and 50: detected. This ‘read two bits’
- Page 51 and 52: in Figure 2.15. Alternatively, the
- Page 53 and 54: of the bit, then write the desired
- Page 55 and 56: 2.4.2 Device Functions and Typical
- Page 57 and 58: and development (R&D) investments b
- Page 59 and 60: 2.5 Network Types and Precedents As
- Page 61 and 62: 2.5.2 1 - Wire® Network Topologies
- Page 63 and 64: 2.5.3 1 - Wire® Network Limitation
- Page 65 and 66: with a single selected slave. If an
- Page 67 and 68: user group was founded in March of
- Page 69 and 70: protocol on multiple media for maxi
- Page 71 and 72: ecessive bit and the monitored stat
- Page 73 and 74: specification: Start-Of-Frame, Arbi
6.4 DS1996 Address Registers ..........................................................................................................198<br />
6.5 RXB1CTRL – Receive Buffer 1 Control Register Bit Definitions .............................................202<br />
7.1 FIFO Buffer Memory ...................................................................................................................213<br />
xxiv
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