DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...

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[55] H. Kopetz and G. Bauer, “The Time-Triggered Architecture,” in Proceedings of the IEEE, Volume 91, Issue 1, 2003, Page(s): 112 – 126. [56] E. A. Bretz, “By – Wire Cars Turn the Corner,” in IEEE Spectrum, Volume 38, Issue 4, 2001, Page(s): 68 – 73. [57] A. Albert, “Comparison of Event-Triggered and Time-Triggered Concepts with Regard to Distributed Control systems,” in Embedded World 2004, Nürnberg, February 17 – 19, 2004, Page(s): 235 – 252. [58] R. Obermaisser, “Event-Triggered and Time-Triggered Control Paradigms,” Springer Science and Business Media, 2005, ISBN: 0-387-23043-2. [59] A. Albert and W. Gerth, “Evaluation and Comparison of the Real-Time Performance of CAN and TTCAN,” 9th international CAN in Automation Conference, iCC, Munich, pages 05/01–05/08, 2003. [60] Wikipedia – Defintion of Real-Time Computing. Website: http://en.wikipedia.org/wiki/Real-time_computing. (Accessed on November 17, 2011). [61] S. Zug, M. Schulze, and J. Kaiser, “Latency Analysis for the Cooperation of Event and Time-Triggered Networks,” in IEEE International Workshop on Factory Communication Systems, WCFS 2008, Page(s): 3 – 9. [62] T. Führer, B. Müller, W. Dieterle, F. Hartwich, R. Hugel, and M. Walther, “Time- Triggered Communication on CAN (Time-Triggered CAN – TTCAN).” Website: http://www.can-cia.de/fileadmin/cia/pdfs/technology/fuehrer.pdf. (Accessed on November 17, 2011). [63] Latency Defintion. Website: http://www.linfo.org/latency.html. (Accessed on November 17, 2011). [64] Wikipedia – Definition of Latency (Engineering). Website: http://en.wikipedia.org/wiki/Latency_(engineering). (Accessed on November 17, 2011). [65] Rainbow Layers – Jaco Swart’s website and blog, “Can the CAN bus solve your design problems?” Website: http://www.rainbowlayers.co.nz/portfolio/CAN-bus. (Accessed on February 11, 2010). [66] J.P. Acle, M.S. Reorda, and M. Violante, “Early, Accurate Dependability Analysis of CAN-Based Networked Systems,” in IEEE Design & Test of Computers, Volume 23, Issue 1, Jan. – Feb. 2006, Page(s): 38 – 45. 223
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Page 1 and 2:
DESIGN OF A CUSTOM ASIC INCORPORATI
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ABSTRACT The vast majority of today
Page 5 and 6:
LIST OF ABBREVIATIONS AND SYMBOLS A
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ISO International Organization for
Page 9 and 10:
SI Serial In SO Serial Out SOF Star
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ACKNOWLEDGEMENTS I would like to ex
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2.4 Types of Devices...............
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4.3.5 Communication Speed Different
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5.3.21.1 Synchronization Test (test
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5.3 Resource Utilization...........
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LIST OF FIGURES 2.1 1 - Wire® Netw
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4.12 Read-Data Time Slot...........
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6.4 DS1996 Address Registers ......
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manufacturing process. Structured o
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describes the 1 - Wire® and CAN co
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2.2 1 - Wire® Overview The basis o
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All 1 - Wire® masters described in
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attachments, microcontroller with b
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Figure 2.3 Bidirectional port pin w
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2.3.3 Synthesizable 1 - Wire® Bus
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Figure 2.7 UART/RS232 Serial Port I
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hardware. Through control registers
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Table 2.2 1 - Wire® Bus Operations
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2.3.6 1 - Wire® Search Algorithm F
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detected. This ‘read two bits’
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in Figure 2.15. Alternatively, the
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of the bit, then write the desired
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2.4.2 Device Functions and Typical
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and development (R&D) investments b
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2.5 Network Types and Precedents As
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2.5.2 1 - Wire® Network Topologies
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2.5.3 1 - Wire® Network Limitation
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with a single selected slave. If an
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user group was founded in March of
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protocol on multiple media for maxi
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ecessive bit and the monitored stat
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specification: Start-Of-Frame, Arbi
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Cyclic Redundancy Check (CRC) Field
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Arbitration FieldThe Arbitration Fi
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SOF SOF Bit 28 Bit 27 Arbitration f
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Afterwards it starts transmitting s
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Figure 3.9 Structure of the Interfr
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error occurs, an Error Frame is gen
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Table 3.4 Error Flag Output Timing
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3.5.2 Error-Passive A node becomes
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where tNBT is the Nominal Bit Time
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Figure 3.12 Propagation Delay Betwe
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3.6.4 Synchronization t t t t (3.
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opposite value is inserted into the
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many systems, the bus length will b
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CHAPTER 4 THE CHALLENGES OF INTERFA
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In June 2004, Maxim Integrated Prod
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Wearable sensor technology is a new
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In traditional bus architectures, o
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Figure 4.3 Centralized arbiter with
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For the initial prototype design pr
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the ID of 31 transmits a ‘0’ (d
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Recently, a technique has been prop
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procedure, then the address claim p
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paradigms are prevalent in the desi
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systems possess a higher flexibilit
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fixed identifier and hence a fixed
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348sm Cm 47 8 smbit 11-bit hea
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est-case latency occurs when the bu
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to break the 1 - Wire® network int
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ow, is most critical for power deli
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computations have device-specific p
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Table 4.7 Example results with N 2
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4.3.5 Communication Speed Different
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anging” a port pin on a microproc
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From Figure 5.1, the block I/O pins
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5.2.2 Command Register In addition
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specifies the selected bit value to
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with i > m. This process is repeate
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Figure 5.6 Interrupt Register. OW_
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the INTR pin will be pulled high si
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master reset occurs. Table 5.2 show
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EN_FOW: Enable Force One Wire. Sett
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READ_ROM - Used to read the 64-bit
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5.2.8.1 Single Search ROM (single_s
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5.2.8.3 Scratchpad Memory (scratchp
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5.2.8.4 Command Recognition (cmd_re
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TBF - The Transmit Buffer provides
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compensate for the propagation dela
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Figure 5.15 CAN Module memory map [
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‘0’, fast speed mode will be us
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COMP-SEL: Comparator Select. When t
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Figure 5.18 CAN Status Register. B
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that buffer is given to the CPU and
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Acceptance Mask Registers (accepted
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SJW1, SJW0: Synchronization Jump Wi
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TSEG22 - TSEG10: Time Segment Bits.
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The transmit clock (ttxclk) is used
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5.3.13 CAN Module Transmit Buffer I
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Figure 5.28 CAN Transmit Data Segme
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5.3.20 CAN Node Overview As stated
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Read Digital InputsRead the value o
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the clock high time is either 5 µs
Page 197 and 198: Yes Perform A/D Conversion on AN0 W
Page 199 and 200: and GP2 and GP5 as outputs. With th
Page 201 and 202: external INT pin, and then branches
Page 203 and 204: Read MCP2515 Rx Buffer for Digital
Page 205 and 206: When a valid message is received, t
Page 207 and 208: Table 5.19 Resource Utilization. Re
Page 209 and 210: For this test, only one CAN node wa
Page 211 and 212: an Error Frame to be generated. Aft
Page 213 and 214: messages, acknowledge messages, or
Page 215 and 216: 5.3.21.4 Send Basic Frame Test (sen
Page 217 and 218: going from one node to 30 nodes (se
Page 219 and 220: Table 6.1 Resource Utilization. Rev
Page 221 and 222: 6.2.1 Test Verification and Overvie
Page 223 and 224: has read access to this register. T
Page 225 and 226: system configuration used for this
Page 227 and 228: or not depends on the number of rec
Page 229 and 230: 6.4. There are two receiving CAN no
Page 231 and 232: CHAPTER 7 CONCLUSIONS AND FUTURE WO
Page 233 and 234: a communication bus reset will occu
Page 235 and 236: For the synthesizable CAN Controlle
Page 237 and 238: additional CAN nodes were added to
Page 239 and 240: Fall-Through Stack A LOW level on t
Page 241 and 242: In conclusion, the prototype system
Page 243 and 244: REFERENCES [1] IBM ASIC Products Ap
Page 245 and 246: [22] “CAN - a brief tutorial for
Page 247: [44] Microchip MCP2515 - Stand-Alon
Page 251 and 252: [88] “Verilog - A Language Refere
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