DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...

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[33] Huang, “PIC® Microcontroller: An Introduction to Software and Hardware Interfacing,” Thomson-Delmar Learning, 2005, pg. 508, ISBN: 1-4018-3967-3. [34] Huang, “The HCS12/9S12: An Introduction to Software and Hard Interfacing,” Thomson-Delmar Learning, 2006, pg. 494, ISBN: 1-4018-9812-2. [35] Xilinx LogiCORE IP XPS Serial Perpiheral Interface (SPI) (v2.02a) Product Specification DS570, June 22, 2011. Website: http://www.xilinx.com/support/documentation/ip_documentation/xps_spi.pdf. (Accessed on November 17, 2011). [36] Altera Corporation Application Note 184: “Simultaneous Multi-Mastering with the Avalon Bus,” Version 1.1, April 2002. Website: http://www.altera.ru/Disks/Altera Documentation Library/literature/an/an184.pdf. (Accessed on November 17, 2011). [37] Altera Corporation, “SOPC User Builder Guide,” December 2010. Website: http://www.altera.com/literature/ug/ug_sopc_builder.pdf. (Accessed on November 17, 2011). [38] M. Abd-El-Barr and H. El-Rewini, “Fundamentals of Computer Organization and Architecture,” John Wiley and Sons, 2005, pp. 179 – 180, ISBN: 0-471-46741-3. [39] M. van Osch and S. Smolka, “Finite-State Analysis of the CAN Bus Protocol,” in Proceedings of the 6 th IEEE International Symposium on High Assurance Systems Engineering (HASE ’01), 22 – 24 October 2001, Page(s): 42 – 52. [40] Y. Yellambalase and M. Choi, “Automatic Node Discovery in CAN (Controller Area Network) Controllers Using Reserved Identifier Bits,” IMTC 2007 – Instrumentation and Measurement Technology Conference, May 1 – 3, 2007. [41] G. Cena and A. Valenzano, “A Protocol for Automatic Node Discovery in CANOpen Networks,” in IEEE Transactions on Industrial Electronics, Volume 50, Number 3, June 2003, Page(s): 419 – 430. [42] Microchip PIC12C67X – 8 – Pin, 8 – Bit CMOS Microcontroller with A/D Converter and EEPROM Data Memory Datasheet. Website: http://ww1.microchip.com/downloads/en/DeviceDoc/30561b.pdf. (Accessed on November 17, 2011). [43] O. Pfeiffer, “Selecting a CAN Controller”. Website: http://www.esacademy.com/en/library/technical-articles-and-documents/can-andcanopen/selecting-a-can-controller.html. (Accessed on November 17, 2011). 221
[44] Microchip MCP2515 – Stand-Alone CAN Controller With SPI Interface Datasheet. Website: http://ww1.microchip.com/downloads/en/devicedoc/21801e.pdf. (Accessed on November 29, 2011). [45] Microchip MCP 2551 – High-Speed CAN Transceiver Datasheet. Website: http://ww1.microchip.com/downloads/en/DeviceDoc/21667f.pdf. (Accessed on November 17, 2011). [46] Microchip MCP 2515 – Stand-Alone CAN Controller with SPI Interface Datasheet. Website: http://ww1.microchip.com/downloads/en/DeviceDoc/21801F.pdf. (Accessed on November 17, 2011). [47] Microchip Application Note AN215: “A Simple CAN Node using the MCP2515 and PIC12C67X,” November 8, 2010. Website: http://ww1.microchip.com/downloads/en/AppNotes/00215c.pdf. (Accessed on November 17, 2011). [48] P. Hank and E. Jӧhnk, Philips Semiconductors Application Note AN97067: “SJA 1000 Stand – Alone CAN Controller,” December 15, 1997. Website: http://www.nxp.com/documents/application_note/AN97076.pdf. (Accessed on November 17, 2011). [49] K. W. Tindell, A. Burns, and A. J. Wellings, “Calculating Controller Area Network (CAN) Messages Response Times,” in Control Engineering Practice, Colume 3, Number 8, pp. 1163 – 1169, 1995. [50] K. W. Tindell, H. Hansson, and A. J. Wellings, “Analysing Real-Time Communications: Controller Area Network (CAN),” in Proceedings Real-Time Systems Symposium, 1994, pp. 259 – 263. [51] R. Obermaisser and D. Riezler, “HIS/Vector CAN Driver API on Top of a Time- Triggered Communication Protocol”, 07AE – 290, in SAE International, 2007. [52] J. Rushby, “Bus Architectures for Safety-Critical Embedded Systems,” in Proceedings of the 1 st Workshop on Embedded Software, October 2001. [53] H. Kopetz, “Why Time-Triggered Architectures will Succeed in Large Hard Real-Time Systems,” in Proceedings of the Fifth IEEE Computer Society Workshop on Future Trands of Distributed Computing systems, 1995, Page(s): 2 – 9. [54] FlexRay Consortium. BMW AG, DaimlerChrysler AG, General Motors Corporation, Freescale GmbH, Philips GmbH, Robert Bosch GmbH, and Volkswagen AG. FlexRay Requirements Specification Version 2.1, December 2005. 222
Page 1 and 2:
DESIGN OF A CUSTOM ASIC INCORPORATI
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ABSTRACT The vast majority of today
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LIST OF ABBREVIATIONS AND SYMBOLS A
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ISO International Organization for
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SI Serial In SO Serial Out SOF Star
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ACKNOWLEDGEMENTS I would like to ex
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2.4 Types of Devices...............
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4.3.5 Communication Speed Different
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5.3.21.1 Synchronization Test (test
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5.3 Resource Utilization...........
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LIST OF FIGURES 2.1 1 - Wire® Netw
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4.12 Read-Data Time Slot...........
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6.4 DS1996 Address Registers ......
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manufacturing process. Structured o
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describes the 1 - Wire® and CAN co
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2.2 1 - Wire® Overview The basis o
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All 1 - Wire® masters described in
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attachments, microcontroller with b
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Figure 2.3 Bidirectional port pin w
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2.3.3 Synthesizable 1 - Wire® Bus
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Figure 2.7 UART/RS232 Serial Port I
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hardware. Through control registers
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Table 2.2 1 - Wire® Bus Operations
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2.3.6 1 - Wire® Search Algorithm F
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detected. This ‘read two bits’
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in Figure 2.15. Alternatively, the
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of the bit, then write the desired
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2.4.2 Device Functions and Typical
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and development (R&D) investments b
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2.5 Network Types and Precedents As
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2.5.2 1 - Wire® Network Topologies
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2.5.3 1 - Wire® Network Limitation
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with a single selected slave. If an
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user group was founded in March of
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protocol on multiple media for maxi
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ecessive bit and the monitored stat
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specification: Start-Of-Frame, Arbi
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Cyclic Redundancy Check (CRC) Field
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Arbitration FieldThe Arbitration Fi
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SOF SOF Bit 28 Bit 27 Arbitration f
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Afterwards it starts transmitting s
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Figure 3.9 Structure of the Interfr
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error occurs, an Error Frame is gen
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Table 3.4 Error Flag Output Timing
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3.5.2 Error-Passive A node becomes
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where tNBT is the Nominal Bit Time
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Figure 3.12 Propagation Delay Betwe
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3.6.4 Synchronization t t t t (3.
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opposite value is inserted into the
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many systems, the bus length will b
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CHAPTER 4 THE CHALLENGES OF INTERFA
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In June 2004, Maxim Integrated Prod
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Wearable sensor technology is a new
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In traditional bus architectures, o
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Figure 4.3 Centralized arbiter with
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For the initial prototype design pr
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the ID of 31 transmits a ‘0’ (d
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Recently, a technique has been prop
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procedure, then the address claim p
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paradigms are prevalent in the desi
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systems possess a higher flexibilit
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fixed identifier and hence a fixed
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348sm Cm 47 8 smbit 11-bit hea
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est-case latency occurs when the bu
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to break the 1 - Wire® network int
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ow, is most critical for power deli
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computations have device-specific p
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Table 4.7 Example results with N 2
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4.3.5 Communication Speed Different
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anging” a port pin on a microproc
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From Figure 5.1, the block I/O pins
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5.2.2 Command Register In addition
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specifies the selected bit value to
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with i > m. This process is repeate
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Figure 5.6 Interrupt Register. OW_
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the INTR pin will be pulled high si
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master reset occurs. Table 5.2 show
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EN_FOW: Enable Force One Wire. Sett
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READ_ROM - Used to read the 64-bit
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5.2.8.1 Single Search ROM (single_s
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5.2.8.3 Scratchpad Memory (scratchp
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5.2.8.4 Command Recognition (cmd_re
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TBF - The Transmit Buffer provides
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compensate for the propagation dela
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Figure 5.15 CAN Module memory map [
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‘0’, fast speed mode will be us
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COMP-SEL: Comparator Select. When t
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Figure 5.18 CAN Status Register. B
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that buffer is given to the CPU and
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Acceptance Mask Registers (accepted
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SJW1, SJW0: Synchronization Jump Wi
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TSEG22 - TSEG10: Time Segment Bits.
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The transmit clock (ttxclk) is used
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5.3.13 CAN Module Transmit Buffer I
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Figure 5.28 CAN Transmit Data Segme
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5.3.20 CAN Node Overview As stated
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Read Digital InputsRead the value o
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Page 197 and 198: Yes Perform A/D Conversion on AN0 W
Page 199 and 200: and GP2 and GP5 as outputs. With th
Page 201 and 202: external INT pin, and then branches
Page 203 and 204: Read MCP2515 Rx Buffer for Digital
Page 205 and 206: When a valid message is received, t
Page 207 and 208: Table 5.19 Resource Utilization. Re
Page 209 and 210: For this test, only one CAN node wa
Page 211 and 212: an Error Frame to be generated. Aft
Page 213 and 214: messages, acknowledge messages, or
Page 215 and 216: 5.3.21.4 Send Basic Frame Test (sen
Page 217 and 218: going from one node to 30 nodes (se
Page 219 and 220: Table 6.1 Resource Utilization. Rev
Page 221 and 222: 6.2.1 Test Verification and Overvie
Page 223 and 224: has read access to this register. T
Page 225 and 226: system configuration used for this
Page 227 and 228: or not depends on the number of rec
Page 229 and 230: 6.4. There are two receiving CAN no
Page 231 and 232: CHAPTER 7 CONCLUSIONS AND FUTURE WO
Page 233 and 234: a communication bus reset will occu
Page 235 and 236: For the synthesizable CAN Controlle
Page 237 and 238: additional CAN nodes were added to
Page 239 and 240: Fall-Through Stack A LOW level on t
Page 241 and 242: In conclusion, the prototype system
Page 243 and 244: REFERENCES [1] IBM ASIC Products Ap
Page 245: [22] “CAN - a brief tutorial for
Page 249 and 250: [67] K. Tindell and A. Burns, “Gu
Page 251 and 252: [88] “Verilog - A Language Refere
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