DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...

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[12] Maxim Semiconductor DS2480B – Serial to 1 – Wire® Line Driver Datasheet, 19-5047, Revision 3, May 2010. Website: http://datasheets.maxim-ic.com/en/ds/DS2480B.pdf. (Accessed on November 17, 2011). [13] Maxim Semiconductor Single-Channel 1 – Wire® Master, DS2482 – 100 Product Datasheet, 19-4930, Revision 8, November 2009. Website: http://datasheets.maximic.com/en/ds/DS2482-100.pdf. (Accessed on November 17, 2011). [14] Maxim Semiconductor Single-Channel 1 – Wire® Master with Sleep Mode, DS2482 – 101 Product Datasheet, 19-4931, Revision 3, November 2010. Website: http://datasheets.maxim-ic.com/en/ds/DS2482-101.pdf. (Accessed on November 17, 2011). [15] Maxim Semiconductor Eight-Channel 1 – Wire® Master with Sleep Mode, DS2482 – 800 Product Datasheet, 19-4932, Revision 3, November 2009. Website: http://datasheets.maxim-ic.com/en/ds/DS2482-800.pdf. (Accessed on November 17, 2011). [16] Maxim Application Note 187: “1 – Wire® Search Algorithm,” March 28, 2002. Website: http://pdfserv.maxim-ic.com/en/an/AN187.pdf. (Accessed November 17, 2011). [17] Maxim Application Note 27: “Understanding and Using Cyclic Redundancy Checks with Maxim iButton Products,” March 29, 2001. Website: http://pdfserv.maximic.com/en/an/AN27.pdf. (Accessed on November 17, 2011). [18] D. Mannisto, M. Dawson (Machine Bus Technology), “An Overview of Controller Area Network (CAN) Technology,” November 12, 2003. Website: http://www.parallax.com/dl/docs/prod/comm/cantechovew.pdf. (Accessed on November 17, 2011). [19] Renesas Electronics Corporation Application Note: “Introduction to CAN.” Website: http://documentation.renesas.com/eng/products/mpumcu/apn/rej05b0804_m16cap.pdf. (Accessed on November 17, 2011). [20] BOSCH CAN Specification Version 2.0. Website: http://esd.cs.ucr.edu/webres/can20.pdf. (Accessed on November 17, 2011). [21] K. Pazul (Microchip Technology, Inc.), Microchip Application Note AN713: “Controller Area Network (CAN) Basics,” September 16, 2005. Website: http://ww1.microchip.com/downloads/en/AppNotes/00713a.pdf. (Accessed on November 17, 2011). 219
[22] “CAN – a brief tutorial for Embedded Engineers,” COMSOL – Computer Solutions Ltd. Website: http://www.computersolutions.co.uk/info/Embedded_tutorials/can_tutorial.htm. (Accessed on November 17, 2011). [23] S. Robb (Freescale Semiconductor), Freescale Semiconductor Application Note AN1798: “CAN Bit Timing Requirement.” Website: http://www.freescale.com/files/microcontrollers/doc/app_note/AN1798.pdf. (Accessed on November 17, 2011). [24] L. M. Pinho, F. Vasques, and E. Tovar, “Integrating Inaccessibility in Response Time Analysis of CAN Networks,” in Proceeding of the 2000 IEEE International Workshop on Factory Communication Systems, 2000, Page(s): 77 – 84. [25] K. Zuberi and K. Shin, “Scheduling Messages on Controller Area Network for Real-Time CIM Applications,, in IEEE Transactions on Robotics and Automation, Volume 13, Number 2, Page(s): 310 – 314, 1997. [26] Rockwell Automation, “DeviceNet Product Overview,” Publication DN – 2.5, Rockwell, 1997. Website: http://www.pacpro.com/upload/data/Rockwell%20Networks/DeviceNET/hardware/Devic eNet_ProdustOverview_Dn25.pdf. (Accessed on November 17, 2011). [27] L.-B. Fredriksson, “CAN for Critical Embedded Automotive Networks,” in IEEE Micro, Volume 22, Issue 4, 2002, Page(s): 28 – 35. [28] H. Kopetz, “Real-Time Systems Design Principles for Distributed Embedded Applications,” Kluwer Academic, Boston, 1997. [29] R. Obermaisser, “Ordering Messages in Virtual CAN Networks,” in the 12 th IEEE International Conference on Electronics, Circuits and Systems, 2005. ICECS 2005, Page(s): 1 – 4. [30] J. Vial and J. Dixon, “Monitoring Battery System for Electric Vehicle, Based on “One Wire” Technology,” Website: http://web.ing.puc.cl/~power/paperspdf/dixon/64a.pdf. (Accessed on November 17, 2011). [31] Eureka Prometheus Project. Website: http://en.wikipedia.org/wiki/EUREKA_Prometheus_Project. (Accessed on November 17, 2011). [32] B. Linke, Maxim Application Note 3967: “Selecting a Serial Bus,”January 30, 2007. Website: http://pdfserv.maxim-ic.com/en/an/AN3967.pdf. (Accessed on November 17, 2011). 220
Page 1 and 2:
DESIGN OF A CUSTOM ASIC INCORPORATI
Page 3 and 4:
ABSTRACT The vast majority of today
Page 5 and 6:
LIST OF ABBREVIATIONS AND SYMBOLS A
Page 7 and 8:
ISO International Organization for
Page 9 and 10:
SI Serial In SO Serial Out SOF Star
Page 11 and 12:
ACKNOWLEDGEMENTS I would like to ex
Page 13 and 14:
2.4 Types of Devices...............
Page 15 and 16:
4.3.5 Communication Speed Different
Page 17 and 18:
5.3.21.1 Synchronization Test (test
Page 19 and 20:
5.3 Resource Utilization...........
Page 21 and 22:
LIST OF FIGURES 2.1 1 - Wire® Netw
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4.12 Read-Data Time Slot...........
Page 25 and 26:
6.4 DS1996 Address Registers ......
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manufacturing process. Structured o
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describes the 1 - Wire® and CAN co
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2.2 1 - Wire® Overview The basis o
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All 1 - Wire® masters described in
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attachments, microcontroller with b
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Figure 2.3 Bidirectional port pin w
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2.3.3 Synthesizable 1 - Wire® Bus
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Figure 2.7 UART/RS232 Serial Port I
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hardware. Through control registers
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Table 2.2 1 - Wire® Bus Operations
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2.3.6 1 - Wire® Search Algorithm F
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detected. This ‘read two bits’
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in Figure 2.15. Alternatively, the
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of the bit, then write the desired
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2.4.2 Device Functions and Typical
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and development (R&D) investments b
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2.5 Network Types and Precedents As
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2.5.2 1 - Wire® Network Topologies
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2.5.3 1 - Wire® Network Limitation
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with a single selected slave. If an
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user group was founded in March of
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protocol on multiple media for maxi
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ecessive bit and the monitored stat
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specification: Start-Of-Frame, Arbi
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Cyclic Redundancy Check (CRC) Field
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Arbitration FieldThe Arbitration Fi
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SOF SOF Bit 28 Bit 27 Arbitration f
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Afterwards it starts transmitting s
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Figure 3.9 Structure of the Interfr
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error occurs, an Error Frame is gen
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Table 3.4 Error Flag Output Timing
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3.5.2 Error-Passive A node becomes
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where tNBT is the Nominal Bit Time
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Figure 3.12 Propagation Delay Betwe
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3.6.4 Synchronization t t t t (3.
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opposite value is inserted into the
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many systems, the bus length will b
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CHAPTER 4 THE CHALLENGES OF INTERFA
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In June 2004, Maxim Integrated Prod
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Wearable sensor technology is a new
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In traditional bus architectures, o
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Figure 4.3 Centralized arbiter with
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For the initial prototype design pr
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the ID of 31 transmits a ‘0’ (d
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Recently, a technique has been prop
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procedure, then the address claim p
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paradigms are prevalent in the desi
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systems possess a higher flexibilit
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fixed identifier and hence a fixed
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348sm Cm 47 8 smbit 11-bit hea
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est-case latency occurs when the bu
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to break the 1 - Wire® network int
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ow, is most critical for power deli
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computations have device-specific p
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Table 4.7 Example results with N 2
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4.3.5 Communication Speed Different
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anging” a port pin on a microproc
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From Figure 5.1, the block I/O pins
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5.2.2 Command Register In addition
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specifies the selected bit value to
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with i > m. This process is repeate
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Figure 5.6 Interrupt Register. OW_
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the INTR pin will be pulled high si
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master reset occurs. Table 5.2 show
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EN_FOW: Enable Force One Wire. Sett
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READ_ROM - Used to read the 64-bit
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5.2.8.1 Single Search ROM (single_s
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5.2.8.3 Scratchpad Memory (scratchp
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5.2.8.4 Command Recognition (cmd_re
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TBF - The Transmit Buffer provides
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compensate for the propagation dela
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Figure 5.15 CAN Module memory map [
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‘0’, fast speed mode will be us
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COMP-SEL: Comparator Select. When t
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Figure 5.18 CAN Status Register. B
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that buffer is given to the CPU and
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Acceptance Mask Registers (accepted
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SJW1, SJW0: Synchronization Jump Wi
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TSEG22 - TSEG10: Time Segment Bits.
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The transmit clock (ttxclk) is used
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5.3.13 CAN Module Transmit Buffer I
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Figure 5.28 CAN Transmit Data Segme
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5.3.20 CAN Node Overview As stated
Page 193 and 194: Read Digital InputsRead the value o
Page 195 and 196: the clock high time is either 5 µs
Page 197 and 198: Yes Perform A/D Conversion on AN0 W
Page 199 and 200: and GP2 and GP5 as outputs. With th
Page 201 and 202: external INT pin, and then branches
Page 203 and 204: Read MCP2515 Rx Buffer for Digital
Page 205 and 206: When a valid message is received, t
Page 207 and 208: Table 5.19 Resource Utilization. Re
Page 209 and 210: For this test, only one CAN node wa
Page 211 and 212: an Error Frame to be generated. Aft
Page 213 and 214: messages, acknowledge messages, or
Page 215 and 216: 5.3.21.4 Send Basic Frame Test (sen
Page 217 and 218: going from one node to 30 nodes (se
Page 219 and 220: Table 6.1 Resource Utilization. Rev
Page 221 and 222: 6.2.1 Test Verification and Overvie
Page 223 and 224: has read access to this register. T
Page 225 and 226: system configuration used for this
Page 227 and 228: or not depends on the number of rec
Page 229 and 230: 6.4. There are two receiving CAN no
Page 231 and 232: CHAPTER 7 CONCLUSIONS AND FUTURE WO
Page 233 and 234: a communication bus reset will occu
Page 235 and 236: For the synthesizable CAN Controlle
Page 237 and 238: additional CAN nodes were added to
Page 239 and 240: Fall-Through Stack A LOW level on t
Page 241 and 242: In conclusion, the prototype system
Page 243: REFERENCES [1] IBM ASIC Products Ap
Page 247 and 248: [44] Microchip MCP2515 - Stand-Alon
Page 249 and 250: [67] K. Tindell and A. Burns, “Gu
Page 251 and 252: [88] “Verilog - A Language Refere
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