DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...

Table 7.1 FIFO Buffer Memory Pin Names and Descriptions.
Pin Name Description
SIC Serial Input Clock
SIE Serial Input Enable
TTS Transfer to Stack Input
MR Master Reset
SOE Serial Output Enable
TOS Transfer Out Serial
SOC Serial Output Clock
DS
QS
Serial Data Input
Serial Data Output
ORE Output Register Empty
IRF Input Register Full
Another option that was considered regarding the FIFO buffer was to integrate it directly
into the synthesizable CAN Controller. Even though the CAN Controller is fully functional
concerning both standard and extended data frames, it is not perfect and by no means capable of
handling hot-swapping of CAN nodes. Perhaps with more testing and debugging, especially
dealing with hot-swapping this idea might be worth returning to and trying to integrate as part of
the CAN Controller.
Although not implemented, considerable thought was also given to the idea of
implementing bi-directional (full-duplex) communication in the prototype system. This would
allow data to be transferred from the CAN network to the 1 – Wire® network and vice versa
simultaneously. This would greatly increase the throughput of the entire system and also system
marketability.
215