DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...
DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ... DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...
Figure 7.1 FIFO Buffer Memory [101]. These three sections operate asynchronously and are virtually independent of one another: Input Register (Data Entry) the Input Register receives data in bit-serial form and stores this data until it is sent to the fall-through stack. It also generates the necessary status and control signals. Data on the Serial Data line (DS) input is serially entered into a shift register on each HIGH-TO-LOW transition of the SIC input when the Serial Input Enable ( SIE ) signal is LOW. 213
Fall-Through Stack A LOW level on the Transfer to Stack ( TTS ) input initiates a fall-through action; if the top location of the stack is empty, data is loaded into the stack and the input register is reinitialized. Thus, automatic FIFO action is achieved by connecting the IRF output to the TTS input. An RS-type flip-flop (the initialization flip-flop) in the control section records the fact that data has been transferred to the stack. This prevents multiple entry of the same word into the stack even though IRF and TTS may still be LOW. Once in the stack, data falls through automatically, pausing only when it is necessary to wait for an empty next location. Output Register The Output Register receives 4-bit data words from the bottom stack location, stores them, and outputs data on a TRI-STATE serial data bus. The output section generates and receives the necessary status and control signals. When the FIFO is empty after a LOW is applied to the MR input, the ORE output is LOW. After data has been entered into the FIFO and has fallen through to the bottom stack location, it is transferred into the output register if the TOS input is LOW. As a result of the data transfer, ORE goes HIGH, indicating that valid data is in the register. 214
- Page 187 and 188: 5.3.13 CAN Module Transmit Buffer I
- Page 189 and 190: Figure 5.28 CAN Transmit Data Segme
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- Page 203 and 204: Read MCP2515 Rx Buffer for Digital
- Page 205 and 206: When a valid message is received, t
- Page 207 and 208: Table 5.19 Resource Utilization. Re
- Page 209 and 210: For this test, only one CAN node wa
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- Page 213 and 214: messages, acknowledge messages, or
- Page 215 and 216: 5.3.21.4 Send Basic Frame Test (sen
- Page 217 and 218: going from one node to 30 nodes (se
- Page 219 and 220: Table 6.1 Resource Utilization. Rev
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- Page 223 and 224: has read access to this register. T
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- Page 237: additional CAN nodes were added to
- Page 241 and 242: In conclusion, the prototype system
- Page 243 and 244: REFERENCES [1] IBM ASIC Products Ap
- Page 245 and 246: [22] “CAN - a brief tutorial for
- Page 247 and 248: [44] Microchip MCP2515 - Stand-Alon
- Page 249 and 250: [67] K. Tindell and A. Burns, “Gu
- Page 251 and 252: [88] “Verilog - A Language Refere
Figure 7.1 FIFO Buffer Memory [101].<br />
These three sections operate asynchronously and are virtually independent of one another:<br />
Input Register (Data Entry) the Input Register receives data in bit-serial form and<br />
stores this data until it is sent to the fall-through stack. It also generates the necessary<br />
status and control signals. Data on the Serial Data line (DS) input is serially entered<br />
into a shift register on each HIGH-TO-LOW transition of the SIC input when the<br />
Serial Input Enable ( SIE ) signal is LOW.<br />
213
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