DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...

additional CAN nodes were added to the system. It should be noted that no failures were
observed when only requesting data from an individual CAN node.
For the vast majority of failures observed while conducting tests on the combined
prototype system, there is no doubt that the system would greatly benefit from the addition of
either a FIFO or prioritized FIFO buffer. Although not implemented as an integral part of the
final design, considerable research was done on this solution. A proposed FIFO buffer based on
a 74F433 FIFO Buffer Memory IC [101] from Fairchild Semiconductor is presented here. Its
purpose would be to provide seamless, asynchronous communication between the 1 – Wire® and
CAN networks. It might even be a possibility that the addition of a FIFO or prioritized FIFO
buffer and a delay timer would solve all of the failure rates seen in the testing of the combined
system.
The FIFO Buffer Memory is organized as 64 words by 4-bits and may be expanded to
any number of words or any number of bits in multiples of four. This allows data to be entered
or extracted asynchronously in serial form. Figure 7.1 shows a block diagram of the FIFO
Buffer Memory section and Table 7.1 gives a brief description of the pin names. It consists of
three major sections:
An Input Register with serial data inputs, as well as control inputs and outputs for input
handshaking and expansion.
A 4-bit-wide, 64-word-deep fall-through stack with self-contained control logic.
An Output Register with serial data outputs, as well as control inputs and outputs for
output handshaking and expansion.
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