DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...
DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ... DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...
known that many CAN transceivers on the market today have very low output impedance when unpowered. This causes the device to sink any signal present on the bus and effectively shuts down all data transmission. One possible solution might be to perform this exact test again but with a different CAN transceiver on each node. Texas Instruments has a transceiver, SN65HVD1050 [100], which according to the data sheet, should work to solve this problem. According to the data sheet, the HVD1050’s bus pins are biased internally to a high-impedance recessive state. This provides for a power-up into a known recessive condition without disturbing ongoing bus communication. It also maintains the integrity of the bus when power or ground is added to or removed from the circuit [100]. Another possible solution is to add additional hardware to the entire CAN bus system, in the form of a bus utilization monitor and data packet logger. Clearly, more time and testing are needed to find a viable solution to this problem. This is important since the ability to plug directly into a currently operating system becomes a valued asset in many CAN applications. For the remaining two tests, send_frame_basic and send_frame_extended, failures are again noted when hot-swapping of nodes was attempted. As previously discussed, more testing is needed, plus the possibility of swapping out the CAN transceiver used on each node, to find a solution and prevent having to perform a hard reset each time hot-swapping is attempted. The prevention of such failures would be a very beneficial feature to any CAN node system, especially for safety-critical networks. It might prove worthwhile for future modifications to consider writing testbench code for tests such as a Reset Mode test and Bus-Off Recovery test. Such tests might provide some insight to possible hot-swapping failures. 209
For the synthesizable CAN Controller, there was an additional test considered but never fully implemented: self_reception_request test. In this test, there are two different modes of operation. First, the CAN module performs an internal loop back (default), which can be used for self-test operation. In this mode, a dummy Acknowledge bit is provided, thereby eliminating the need for another node on the bus to provide the Acknowledge bit (i.e. the module treats its own transmitted message as a message received from a remote node). The rx input pin is ignored and the tx output pin goes to the recessive state (logic ‘1’). Both transmit and receive interrupts are generated. Alternatively, if the user desires, the current message can be queued for transmission without disabling the receiver. It will receive the message only if the Acceptance Filter recognizes the message ID. This test was originally considered as a part of a plan to also implement a FIFO or prioritized FIFO buffer in the synthesizable CAN Controller. But after much time and consideration it was thought that a better approach would be to implement a FIFO or prioritized FIFO buffer as a separate entity in the design and not integrate it as part of the CAN Controller. So for this reason development and implementation of this test was dropped. From the test results of those performed in Chapter 6, the combined 1 – Wire® to CAN prototype system clearly needs more debugging and testing before becoming a fully-functional production prototype. This is evident from the failures noted in Tables 6.2 and 6.4 as a result of the two tests performed. Even though neither of the two tests performed had a failure from a catastrophic point of view, both tests had failures concerning lost CAN bus messages when trying to run 1 – Wire® devices in overdrive speed and also when trying to hot-swap 1 – Wire® devices. As stated previously, this is primarily attributed to the extra steps required to get all 1 – Wire® devices into overdrive mode. This is still a big problem especially if the system is going 210
- Page 183 and 184: TSEG22 - TSEG10: Time Segment Bits.
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- Page 189 and 190: Figure 5.28 CAN Transmit Data Segme
- Page 191 and 192: 5.3.20 CAN Node Overview As stated
- Page 193 and 194: Read Digital InputsRead the value o
- Page 195 and 196: the clock high time is either 5 µs
- Page 197 and 198: Yes Perform A/D Conversion on AN0 W
- Page 199 and 200: and GP2 and GP5 as outputs. With th
- Page 201 and 202: external INT pin, and then branches
- Page 203 and 204: Read MCP2515 Rx Buffer for Digital
- Page 205 and 206: When a valid message is received, t
- Page 207 and 208: Table 5.19 Resource Utilization. Re
- Page 209 and 210: For this test, only one CAN node wa
- Page 211 and 212: an Error Frame to be generated. Aft
- Page 213 and 214: messages, acknowledge messages, or
- Page 215 and 216: 5.3.21.4 Send Basic Frame Test (sen
- Page 217 and 218: going from one node to 30 nodes (se
- Page 219 and 220: Table 6.1 Resource Utilization. Rev
- Page 221 and 222: 6.2.1 Test Verification and Overvie
- Page 223 and 224: has read access to this register. T
- Page 225 and 226: system configuration used for this
- Page 227 and 228: or not depends on the number of rec
- Page 229 and 230: 6.4. There are two receiving CAN no
- Page 231 and 232: CHAPTER 7 CONCLUSIONS AND FUTURE WO
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- Page 239 and 240: Fall-Through Stack A LOW level on t
- Page 241 and 242: In conclusion, the prototype system
- Page 243 and 244: REFERENCES [1] IBM ASIC Products Ap
- Page 245 and 246: [22] “CAN - a brief tutorial for
- Page 247 and 248: [44] Microchip MCP2515 - Stand-Alon
- Page 249 and 250: [67] K. Tindell and A. Burns, “Gu
- Page 251 and 252: [88] “Verilog - A Language Refere
known that many CAN transceivers on the market today have very low output impedance<br />
when unpowered. This causes the device to sink any signal present on the bus and effectively<br />
shuts down all data transmission. One possible solution might be to perform this exact test again<br />
but with a different CAN transceiver on each node. Texas Instruments has a transceiver,<br />
SN65HVD1050 [100], which according to the data sheet, should work to solve this problem.<br />
According to the data sheet, the HVD1050’s bus pins are biased internally to a high-impedance<br />
recessive state. This provides for a power-up into a known recessive condition without<br />
disturbing ongoing bus communication. It also maintains the integrity of the bus when power or<br />
ground is added to or removed from the circuit [100]. Another possible solution is to add<br />
additional hardware to the entire CAN bus system, in the form of a bus utilization monitor and<br />
data packet logger. Clearly, more time and testing are needed to find a viable solution to this<br />
problem. This is important since the ability to plug directly into a currently operating system<br />
becomes a valued asset in many CAN applications.<br />
For the remaining two tests, send_frame_basic and send_frame_extended, failures are<br />
again noted when hot-swapping of nodes was attempted. As previously discussed, more testing<br />
is needed, plus the possibility of swapping out the CAN transceiver used on each node, to find<br />
a solution and prevent having to perform a hard reset each time hot-swapping is attempted. The<br />
prevention of such failures would be a very beneficial feature to any CAN node system,<br />
especially for safety-critical networks. It might prove worthwhile for future modifications to<br />
consider writing testbench code for tests such as a Reset Mode test and Bus-Off Recovery test.<br />
Such tests might provide some insight to possible hot-swapping failures.<br />
209
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