DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...

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As stated in section 5.2.8.3, scratchpad_integrity test, more testing is needed for conclusive evidence on failure rates. In particular more tests need to be performed using multiple 1 – Wire® slave devices of different types. If multiple 1 – Wire® slave devices exist on the 1 – Wire® network and a READ_ROM command (0x33) is issued immediately following the SKIP_ROM command (0xCC), data collision is inevitable on the bus as multiple slaves will try and transmit simultaneously. This is a direct result of open-drain pull-downs, as they will produce a wired-<strong>AND</strong> result. This will more than likely shut the 1 – Wire® network down but perhaps with testing on just this case, it might be possible to at least minimize the failure rate and prevent data loss from occurring. Another area where more testing is needed for all four test cases presented in sections 5.2.8.1 through 5.2.8.4 is the use of both standard and overdrive speed devices coexisting on the same network. Even though the test conducted in section 5.2.8.4, cmd_recognition, used several overdrive commands, there was only a single 1 – Wire® slave device on the network. Additionally hot-swapping was performed and no failures were observed with a single 1 – Wire® device; the same cannot be automatically assumed in the case for multiple 1 – Wire® slaves. This is especially true if both standard and overdrive speed capable devices coexist on the same network. Therefore more testing is needed to ensure reliability and data integrity on the 1 – Wire® network, in the cases of hot-swapping and coexistence of both standard and overdrive speed devices. Even though the time savings is nearly 2.5 times greater at overdrive speeds than at standard speeds, extra care must be taken when hot-swapping slave devices at overdrive speeds. Since hot-swapping slave devices causes a temporary electrical short between DATA and GND, 207
a communication bus reset will occur. This in turn will reset all slave devices operating at overdrive speed back to standard speed. For the combined 1 – Wire® and CAN system, failures will be imminent. More testing and debugging is needed so as to minimized the failure rate as much as possible and also to try and mitigate data loss and/or corruption of both CAN and 1 – Wire® data packets. The synthesizable CAN Controller presented in Chapter 5 is based upon two different models: the Bosch VHDL Reference System is used mostly for a verification tool and the Motorola CAN (MCAN) Module [95 – 97] for its functional and memory map layout. The design is written in Verilog® and tested on an Altera DE2 Development and Education Board using the Quartus II software package. From the five tests executed (test_synchronization, bus_off_test, error_test, send_frame_basic, and send_frame_extended), failures were only noticed when attempting to hot swap a node. Of the three tests where hot-swapping was attempted (error_testSection 5.3.21.3, send_frame_basicSection 5.3.21.4, and send_frame_extendedSection 5.3.21.5), all three tests encountered failures and a hard reset had to be performed for communication to be re-established. For the test conducted in Section 5.3.21.3, error_test, 30 CAN nodes are utilized. More testing and debugging is necessary to find, if one exists, a root cause for the failure of the CAN realized when attempting hot-swapping of CAN nodes. At this time, the only plausible explanation for the failure is believed to be in the CAN transceiver used on each CAN node. Although the data sheet for the MCP2551 [45], used on each CAN node, states that when the device is powered on, CAN_H and CAN_L remain in a high-impedance state until VDD reaches the voltage-level VPORH, it does not give an exact value for this impedance. It is 208
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DESIGN OF A CUSTOM ASIC INCORPORATI
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ABSTRACT The vast majority of today
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LIST OF ABBREVIATIONS AND SYMBOLS A
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ISO International Organization for
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SI Serial In SO Serial Out SOF Star
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ACKNOWLEDGEMENTS I would like to ex
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2.4 Types of Devices...............
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4.3.5 Communication Speed Different
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5.3.21.1 Synchronization Test (test
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5.3 Resource Utilization...........
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LIST OF FIGURES 2.1 1 - Wire® Netw
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4.12 Read-Data Time Slot...........
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6.4 DS1996 Address Registers ......
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manufacturing process. Structured o
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describes the 1 - Wire® and CAN co
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2.2 1 - Wire® Overview The basis o
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All 1 - Wire® masters described in
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attachments, microcontroller with b
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Figure 2.3 Bidirectional port pin w
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2.3.3 Synthesizable 1 - Wire® Bus
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Figure 2.7 UART/RS232 Serial Port I
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hardware. Through control registers
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Table 2.2 1 - Wire® Bus Operations
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2.3.6 1 - Wire® Search Algorithm F
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detected. This ‘read two bits’
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in Figure 2.15. Alternatively, the
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of the bit, then write the desired
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2.4.2 Device Functions and Typical
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and development (R&D) investments b
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2.5 Network Types and Precedents As
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2.5.2 1 - Wire® Network Topologies
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2.5.3 1 - Wire® Network Limitation
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with a single selected slave. If an
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user group was founded in March of
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protocol on multiple media for maxi
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ecessive bit and the monitored stat
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specification: Start-Of-Frame, Arbi
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Cyclic Redundancy Check (CRC) Field
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Arbitration FieldThe Arbitration Fi
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SOF SOF Bit 28 Bit 27 Arbitration f
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Afterwards it starts transmitting s
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Figure 3.9 Structure of the Interfr
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error occurs, an Error Frame is gen
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Table 3.4 Error Flag Output Timing
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3.5.2 Error-Passive A node becomes
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where tNBT is the Nominal Bit Time
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Figure 3.12 Propagation Delay Betwe
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3.6.4 Synchronization t t t t (3.
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opposite value is inserted into the
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many systems, the bus length will b
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CHAPTER 4 THE CHALLENGES OF INTERFA
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In June 2004, Maxim Integrated Prod
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Wearable sensor technology is a new
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In traditional bus architectures, o
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Figure 4.3 Centralized arbiter with
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For the initial prototype design pr
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the ID of 31 transmits a ‘0’ (d
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Recently, a technique has been prop
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procedure, then the address claim p
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paradigms are prevalent in the desi
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systems possess a higher flexibilit
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fixed identifier and hence a fixed
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348sm Cm 47 8 smbit 11-bit hea
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est-case latency occurs when the bu
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to break the 1 - Wire® network int
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ow, is most critical for power deli
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computations have device-specific p
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Table 4.7 Example results with N 2
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4.3.5 Communication Speed Different
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anging” a port pin on a microproc
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From Figure 5.1, the block I/O pins
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5.2.2 Command Register In addition
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specifies the selected bit value to
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with i > m. This process is repeate
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Figure 5.6 Interrupt Register. OW_
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the INTR pin will be pulled high si
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master reset occurs. Table 5.2 show
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EN_FOW: Enable Force One Wire. Sett
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READ_ROM - Used to read the 64-bit
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5.2.8.1 Single Search ROM (single_s
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5.2.8.3 Scratchpad Memory (scratchp
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5.2.8.4 Command Recognition (cmd_re
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TBF - The Transmit Buffer provides
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compensate for the propagation dela
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Figure 5.15 CAN Module memory map [
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‘0’, fast speed mode will be us
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COMP-SEL: Comparator Select. When t
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Figure 5.18 CAN Status Register. B
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that buffer is given to the CPU and
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Acceptance Mask Registers (accepted
Page 181 and 182: SJW1, SJW0: Synchronization Jump Wi
Page 183 and 184: TSEG22 - TSEG10: Time Segment Bits.
Page 185 and 186: The transmit clock (ttxclk) is used
Page 187 and 188: 5.3.13 CAN Module Transmit Buffer I
Page 189 and 190: Figure 5.28 CAN Transmit Data Segme
Page 191 and 192: 5.3.20 CAN Node Overview As stated
Page 193 and 194: Read Digital InputsRead the value o
Page 195 and 196: the clock high time is either 5 µs
Page 197 and 198: Yes Perform A/D Conversion on AN0 W
Page 199 and 200: and GP2 and GP5 as outputs. With th
Page 201 and 202: external INT pin, and then branches
Page 203 and 204: Read MCP2515 Rx Buffer for Digital
Page 205 and 206: When a valid message is received, t
Page 207 and 208: Table 5.19 Resource Utilization. Re
Page 209 and 210: For this test, only one CAN node wa
Page 211 and 212: an Error Frame to be generated. Aft
Page 213 and 214: messages, acknowledge messages, or
Page 215 and 216: 5.3.21.4 Send Basic Frame Test (sen
Page 217 and 218: going from one node to 30 nodes (se
Page 219 and 220: Table 6.1 Resource Utilization. Rev
Page 221 and 222: 6.2.1 Test Verification and Overvie
Page 223 and 224: has read access to this register. T
Page 225 and 226: system configuration used for this
Page 227 and 228: or not depends on the number of rec
Page 229 and 230: 6.4. There are two receiving CAN no
Page 231: CHAPTER 7 CONCLUSIONS AND FUTURE WO
Page 235 and 236: For the synthesizable CAN Controlle
Page 237 and 238: additional CAN nodes were added to
Page 239 and 240: Fall-Through Stack A LOW level on t
Page 241 and 242: In conclusion, the prototype system
Page 243 and 244: REFERENCES [1] IBM ASIC Products Ap
Page 245 and 246: [22] “CAN - a brief tutorial for
Page 247 and 248: [44] Microchip MCP2515 - Stand-Alon
Page 249 and 250: [67] K. Tindell and A. Burns, “Gu
Page 251 and 252: [88] “Verilog - A Language Refere
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