DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...

CHAPTER 7
CONCLUSIONS AND FUTURE WORK
Many of today’s digital designs are implemented using custom ASICs or gate arrays.
Quite often, entire systems can be implemented with only a few ASICs. The use of FPGAs is
also increasing, providing lower cost ASIC-based alternatives to limited production designs. In
general, the proliferation of ASICs and gate arrays in contemporary digital designs is increasing
at a rapid rate. The research encompassed by this work presented a VLSI (Very Large Scale
Integration) design and simulation of a custom ASIC incorporating two communication
protocols, CAN (Controller Area Network) and 1 – Wire®, targeting wearable medical
technology and devices and hybrid-electric vehicle technology applications.
The synthesizable 1 – Wire® Master presented in Chapter 5 is based on the 1 – Wire®
communications protocol by Maxim Semiconductor. The design is written in Verilog® and
tested on an Altera DE2 Development and Education Board using the Quartus II software
package. From the four tests executed (single_search_rom, multi_ow_network,
scratchpad_integrity, and cmd_recognition), no failures were observed even during hot-swapping
of both parasitically and non-parasitically powered slave device. With this being the case, more
testing is needed using standard and overdrive speeds as well as parasitically and non-
parasitically powered devices before finalizing the prototype 1 – Wire® Master.
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