DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...
DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...
DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...
Create successful ePaper yourself
Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.
4.12 Read-Data Time Slot..................................................................................................................107<br />
5.1 one_wm Synthesizable 1 – Wire® Bus Master Block Diagram ..................................................115<br />
5.2 Command Register Bits ...............................................................................................................118<br />
5.3 Search ROM Accelerator Mode Send Bytes ...............................................................................120<br />
5.4 Search ROM Accelerator Mode Response Bytes ........................................................................121<br />
5.5 Transmit/Receive Buffer Register ...............................................................................................122<br />
5.6 Interrupt Register .........................................................................................................................124<br />
5.7 Interrupt Enable Register .............................................................................................................126<br />
5.8 Clock Divisor Register .................................................................................................................127<br />
5.9 Control Register ...........................................................................................................................129<br />
5.10 Single Search ROM Test Setup .................................................................................................134<br />
5.11 Multiple One-Wire Network Test Setup ....................................................................................135<br />
5.12 Scratchpad Memory Test Setup .................................................................................................137<br />
5.13 CAN Controller Block Diagram ............................................................................................140<br />
5.14 Controller Interface Logic Unit (CIL) .......................................................................................143<br />
5.15 CAN Module memory map....................................................................................................144<br />
5.16 CAN Control Register ............................................................................................................145<br />
5.17 CAN Command Register .......................................................................................................147<br />
5.18 CAN Status Register ..............................................................................................................150<br />
5.19 CAN Interrupt Register ..........................................................................................................152<br />
5.20 CAN Acceptance Code Register ............................................................................................154<br />
5.21 CAN Acceptance Mask Register ...........................................................................................155<br />
xxii