DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...

6.2.1.1 DS1996 Addressing and Memory Layout
Properly communicating with the DS1996 [83] 1 – Wire® devices used in these tests
requires an understanding and explanation of how the memory is organized and how to address
individual pages within the memory. The memory map for a DS1996 [83] is shown in Figure
6.3. At the top of the memory map is a 32-byte page, called the scratchpad. The scratchpad is an
additional page that acts as a buffer when writing to memory. Beneath this are the additional 32-
byte pages of memory. The DS1996 contains 256 pages which comprise the 65,536 bits of
read/write nonvolatile memory.
Figure 6.3 DS1996 iButton Memory Map.
Because of the serial data transfer, the DS1996 employs three address registers, called
TA1, TA2, and E/S as shown in Figure 6.4. Registers TA1 and TA2 must be loaded with the
target address to which the data will be written or from which data will be sent to the 1 – Wire®
Master upon a Read command. Register E/S acts like a byte counter and Transfer Status register.
It is used to verify data integrity with Write commands. Therefore, the 1 – Wire® Master only
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