DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...

DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ... DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...

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6.2 Verification of Combined Prototype System To verify proper operation of the 1 – Wire® and CAN combined prototype system, several test cases are executed, utilizing both regular and overdrive 1 – Wire® communication speeds. For all tests, the hardware used, shown in Figure 6.2, includes the following components: three DS1996 – 64Kb Memory iButtons [83], DS1402-BR8+ 1 – Wire® Network Cable [80], DS1401-4 Front-Panel iButton Holder [81], and two CAN nodes as described in Section 5.3.20. The reason for using the DS1996 64Kb Memory iButtons is that the DS1996 is the largest memory iButton currently in production, and provides 65,536 bits of read/write nonvolatile memory partitioned into 256-bit pages for packetizing data. The equivalent EPROM, DS1986 [99], could just as easily have been used as a suitable replacement except the product is no longer available and therefore is not recommended for new designs. However, the DS1977 [93] could be used as a substitute, especially if security were an issue and password protection were required. Both tests are compiled and simulated using Altera Quartus II 9.1 (32-bit) and ModelSim Altera Starter Edition 6.6c software on a PC executing Windows XP Service Pack 3. All tests are performed extensively while trying to cover all possible combinations of inputs and outputs. The source code for all modules, testbench code, and simulation results are located on the DVD included with this work. Figure 6.2 1 – Wire® & CAN Combined Prototype System. 195

6.2.1 Test Verification and Overview For the tests presented here, all 1 – Wire® devices and CAN nodes are tested at regular speeds (approximately 14 kbps for all 1 – Wire® devices and 10 kbps for all CAN nodes) and overdrive speeds (approximately 140 kbps for all 1 – Wire® devices and 125 kbps for all CAN nodes). Also for this test only two CAN nodes and three DS1996 1 – Wire® devices are used. This was done for easier troubleshooting in case of a catastrophic failure and would make analysis of the data bytes transferred simpler with fewer CAN nodes and 1 – Wire® devices on the bus. Since this was the first time testing the combined system, there was some degree of uncertainty concerning functionality after combining the Verilog® source code of the 1 – Wire® Master and the CAN Module. Combining the source code for the CAN Module and 1 – Wire® Master required additional lines of code to take into account the additional logic registers and logic elements required. For both tests in described Sections 6.2.1.2 and 6.2.1.3, the 1 – Wire Search Algorithm (see Section 2.3.6) is used to discover the 64-bit identification numbers of the DS1996 1 – Wire® devices. Once the identification numbers are known and stored in memory on the 1 – Wire Master, the order in which the numbers are obtained is the order in which the devices are written to. With the DS1996, the offset data byte is used to determine the next byte of memory to which data will be written. When the device memory is full, the next available DS1996 discovered by the 1 – Wire® Search Algorithm is used. This process is repeated for all three DS1996 1 – Wire® devices until the memory of all three devices is full. Then the process is repeated all over again with the next byte of data being written to the first DS1996 1 – Wire® device, overwriting old data as necessary. 196

6.2 Verification of Combined Prototype System<br />

To verify proper operation of the 1 – Wire® and CAN combined prototype system,<br />

several test cases are executed, utilizing both regular and overdrive 1 – Wire® communication<br />

speeds. For all tests, the hardware used, shown in Figure 6.2, includes the following<br />

components: three DS1996 – 64Kb Memory iButtons [83], DS1402-BR8+ 1 – Wire®<br />

Network Cable [80], DS1401-4 Front-Panel iButton Holder [81], and two CAN nodes as<br />

described in Section 5.3.20. The reason for using the DS1996 64Kb Memory iButtons is that<br />

the DS1996 is the largest memory iButton currently in production, and provides 65,536 bits of<br />

read/write nonvolatile memory partitioned into 256-bit pages for packetizing data. The<br />

equivalent EPROM, DS1986 [99], could just as easily have been used as a suitable replacement<br />

except the product is no longer available and therefore is not recommended for new designs.<br />

However, the DS1977 [93] could be used as a substitute, especially if security were an issue and<br />

password protection were required. Both tests are compiled and simulated using Altera Quartus<br />

II 9.1 (32-bit) and ModelSim Altera Starter Edition 6.6c software on a PC executing Windows<br />

XP Service Pack 3. All tests are performed extensively while trying to cover all possible<br />

combinations of inputs and outputs. The source code for all modules, testbench code, and<br />

simulation results are located on the DVD included with this work.<br />

Figure 6.2 1 – Wire® & CAN Combined Prototype System.<br />

195

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