DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...

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3.2 ISO/OSI Reference Model ...........................................................................................................44 3.3 Standard CAN Data Frame Format ..........................................................................................48 3.4 Extended CAN Data Frame Format .........................................................................................51 3.5 Standard and Extended Remote Frame Structures.......................................................................54 3.6 Structure of the Error Frame ........................................................................................................55 3.7 Structure of the Overload Frame..................................................................................................57 3.8 Structure of the Interframe Space (non error-passive nodes) ......................................................57 3.9 Structure of the Interframe Space (error-passive nodes) .............................................................58 3.10 CAN Bus Error States ............................................................................................................63 3.11CAN Bit Segments ..................................................................................................................66 3.12 Propagation Delay Between Nodes ...........................................................................................68 4.1 Centralized arbiter in a daisy-chain scheme ................................................................................82 4.2 Centralized arbiter with independent request and grant lines ......................................................83 4.3 Centralized arbiter with two priority levels (four devices) ..........................................................84 4.4 Decentralized bus arbitration .......................................................................................................84 4.5 CAN node components simplified block diagram ...................................................................88 4.6 CAN Node Message Acceptance Filtering ..............................................................................89 4.7 Address Claim Unit......................................................................................................................90 4.8 Message Queuing Jitter ................................................................................................................98 4.9 Initialization Procedure: Reset and Presence Pulse .....................................................................105 4.10 Write-One Time Slot..................................................................................................................106 4.11 Write-Zero Time Slot .................................................................................................................106 xxi
4.12 Read-Data Time Slot..................................................................................................................107 5.1 one_wm Synthesizable 1 – Wire® Bus Master Block Diagram ..................................................115 5.2 Command Register Bits ...............................................................................................................118 5.3 Search ROM Accelerator Mode Send Bytes ...............................................................................120 5.4 Search ROM Accelerator Mode Response Bytes ........................................................................121 5.5 Transmit/Receive Buffer Register ...............................................................................................122 5.6 Interrupt Register .........................................................................................................................124 5.7 Interrupt Enable Register .............................................................................................................126 5.8 Clock Divisor Register .................................................................................................................127 5.9 Control Register ...........................................................................................................................129 5.10 Single Search ROM Test Setup .................................................................................................134 5.11 Multiple One-Wire Network Test Setup ....................................................................................135 5.12 Scratchpad Memory Test Setup .................................................................................................137 5.13 CAN Controller Block Diagram ............................................................................................140 5.14 Controller Interface Logic Unit (CIL) .......................................................................................143 5.15 CAN Module memory map....................................................................................................144 5.16 CAN Control Register ............................................................................................................145 5.17 CAN Command Register .......................................................................................................147 5.18 CAN Status Register ..............................................................................................................150 5.19 CAN Interrupt Register ..........................................................................................................152 5.20 CAN Acceptance Code Register ............................................................................................154 5.21 CAN Acceptance Mask Register ...........................................................................................155 xxii
Page 1 and 2: DESIGN OF A CUSTOM ASIC INCORPORATI
Page 3 and 4: ABSTRACT The vast majority of today
Page 5 and 6: LIST OF ABBREVIATIONS AND SYMBOLS A
Page 7 and 8: ISO International Organization for
Page 9 and 10: SI Serial In SO Serial Out SOF Star
Page 11 and 12: ACKNOWLEDGEMENTS I would like to ex
Page 13 and 14: 2.4 Types of Devices...............
Page 15 and 16: 4.3.5 Communication Speed Different
Page 17 and 18: 5.3.21.1 Synchronization Test (test
Page 19 and 20: 5.3 Resource Utilization...........
Page 21: LIST OF FIGURES 2.1 1 - Wire® Netw
Page 25 and 26: 6.4 DS1996 Address Registers ......
Page 27 and 28: manufacturing process. Structured o
Page 29 and 30: describes the 1 - Wire® and CAN co
Page 31 and 32: 2.2 1 - Wire® Overview The basis o
Page 33 and 34: All 1 - Wire® masters described in
Page 35 and 36: attachments, microcontroller with b
Page 37 and 38: Figure 2.3 Bidirectional port pin w
Page 39 and 40: 2.3.3 Synthesizable 1 - Wire® Bus
Page 41 and 42: Figure 2.7 UART/RS232 Serial Port I
Page 43 and 44: hardware. Through control registers
Page 45 and 46: Table 2.2 1 - Wire® Bus Operations
Page 47 and 48: 2.3.6 1 - Wire® Search Algorithm F
Page 49 and 50: detected. This ‘read two bits’
Page 51 and 52: in Figure 2.15. Alternatively, the
Page 53 and 54: of the bit, then write the desired
Page 55 and 56: 2.4.2 Device Functions and Typical
Page 57 and 58: and development (R&D) investments b
Page 59 and 60: 2.5 Network Types and Precedents As
Page 61 and 62: 2.5.2 1 - Wire® Network Topologies
Page 63 and 64: 2.5.3 1 - Wire® Network Limitation
Page 65 and 66: with a single selected slave. If an
Page 67 and 68: user group was founded in March of
Page 69 and 70: protocol on multiple media for maxi
Page 71 and 72: ecessive bit and the monitored stat
Page 73 and 74:
specification: Start-Of-Frame, Arbi
Page 75 and 76:
Cyclic Redundancy Check (CRC) Field
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Arbitration FieldThe Arbitration Fi
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SOF SOF Bit 28 Bit 27 Arbitration f
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Afterwards it starts transmitting s
Page 83 and 84:
Figure 3.9 Structure of the Interfr
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error occurs, an Error Frame is gen
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Table 3.4 Error Flag Output Timing
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3.5.2 Error-Passive A node becomes
Page 91 and 92:
where tNBT is the Nominal Bit Time
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Figure 3.12 Propagation Delay Betwe
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3.6.4 Synchronization t t t t (3.
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opposite value is inserted into the
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many systems, the bus length will b
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CHAPTER 4 THE CHALLENGES OF INTERFA
Page 103 and 104:
In June 2004, Maxim Integrated Prod
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Wearable sensor technology is a new
Page 107 and 108:
In traditional bus architectures, o
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Figure 4.3 Centralized arbiter with
Page 111 and 112:
For the initial prototype design pr
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the ID of 31 transmits a ‘0’ (d
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Recently, a technique has been prop
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procedure, then the address claim p
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paradigms are prevalent in the desi
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systems possess a higher flexibilit
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fixed identifier and hence a fixed
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348sm Cm 47 8 smbit 11-bit hea
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est-case latency occurs when the bu
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to break the 1 - Wire® network int
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ow, is most critical for power deli
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computations have device-specific p
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Table 4.7 Example results with N 2
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4.3.5 Communication Speed Different
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anging” a port pin on a microproc
Page 141 and 142:
From Figure 5.1, the block I/O pins
Page 143 and 144:
5.2.2 Command Register In addition
Page 145 and 146:
specifies the selected bit value to
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with i > m. This process is repeate
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Figure 5.6 Interrupt Register. OW_
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the INTR pin will be pulled high si
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master reset occurs. Table 5.2 show
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EN_FOW: Enable Force One Wire. Sett
Page 157 and 158:
READ_ROM - Used to read the 64-bit
Page 159 and 160:
5.2.8.1 Single Search ROM (single_s
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5.2.8.3 Scratchpad Memory (scratchp
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5.2.8.4 Command Recognition (cmd_re
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TBF - The Transmit Buffer provides
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compensate for the propagation dela
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Figure 5.15 CAN Module memory map [
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‘0’, fast speed mode will be us
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COMP-SEL: Comparator Select. When t
Page 175 and 176:
Figure 5.18 CAN Status Register. B
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that buffer is given to the CPU and
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Acceptance Mask Registers (accepted
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SJW1, SJW0: Synchronization Jump Wi
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TSEG22 - TSEG10: Time Segment Bits.
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The transmit clock (ttxclk) is used
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5.3.13 CAN Module Transmit Buffer I
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Figure 5.28 CAN Transmit Data Segme
Page 191 and 192:
5.3.20 CAN Node Overview As stated
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Read Digital InputsRead the value o
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the clock high time is either 5 µs
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Yes Perform A/D Conversion on AN0 W
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and GP2 and GP5 as outputs. With th
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external INT pin, and then branches
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Read MCP2515 Rx Buffer for Digital
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When a valid message is received, t
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Table 5.19 Resource Utilization. Re
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For this test, only one CAN node wa
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an Error Frame to be generated. Aft
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messages, acknowledge messages, or
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5.3.21.4 Send Basic Frame Test (sen
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going from one node to 30 nodes (se
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Table 6.1 Resource Utilization. Rev
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6.2.1 Test Verification and Overvie
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has read access to this register. T
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system configuration used for this
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or not depends on the number of rec
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6.4. There are two receiving CAN no
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CHAPTER 7 CONCLUSIONS AND FUTURE WO
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a communication bus reset will occu
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For the synthesizable CAN Controlle
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additional CAN nodes were added to
Page 239 and 240:
Fall-Through Stack A LOW level on t
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In conclusion, the prototype system
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REFERENCES [1] IBM ASIC Products Ap
Page 245 and 246:
[22] “CAN - a brief tutorial for
Page 247 and 248:
[44] Microchip MCP2515 - Stand-Alon
Page 249 and 250:
[67] K. Tindell and A. Burns, “Gu
Page 251 and 252:
[88] “Verilog - A Language Refere
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