DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...

an Error Frame to be generated. After ten bit time slots, the message is resent with the
proper CRC value to simulate whether all nodes received the message properly.
Acknowledge Error – For this test, the Altera DE2 board checks if the Acknowledge Bit
(which it has sent as a recessive bit) contains a dominant bit. The purpose of this
dominant bit is to acknowledge that at least one node correctly received the message. If
this bit is recessive, then no node received the message properly and an Acknowledge
Error will occur. Both scenarios, recessive and dominant states, are tested to ensure
proper message reception by all CAN nodes. For the recessive state, an Acknowledge
Error occurs and an Error Frame is generated. After ten bit time slots the original
message is resent with a dominant bit in the Acknowledge Field to verify the successful
retransmission of the message.
Form Error – If any node detects a dominant bit in the End of Frame, Interframe Space,
Acknowledge Delimiter or CRC Delimiter, the CAN protocol defines this to be a form
violation and a Form Error is generated. For this test, a dominant bit is placed in each of
the bit positions to cause a Form Error to be generated for each of these conditions. After
waiting for ten bit times, the original message is then resent to all 30 CAN nodes
verifying proper operation.
Bit Error – This situation arises if a transmitter sends a dominant bit and detects a
recessive bit, or if it sends a recessive bit and detects a dominant bit when monitoring the
actual bus level and comparing it to the bit that it has just sent. If a Bit Error is detected,
an Error Frame is generated. To verify this, the actual bit sent is complemented from the
receiver nodes and after ten bit times the bit is sent again in its uncomplemented form.
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