DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...

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Table 5.20 Bus-Off Test (bus_off_test) Results. Speed(kbps) Data Bytes Length of test Messages Sent Messages Rec’d 10 60 min 226,718 0 20 60 min 457,433 0 62.5 60 min 1,413,317 0 125 250 8 60 min 60 min 2,817,783 5,628,518 0 0 500 60 min 11,249,982 0 800 60 min 17,977,528 0 1000 60 min 22,401,991 0 5.3.21.3 Error Test (error_test) CAN nodes have the ability to determine fault conditions and transition to different modes based on the severity of problems being encountered. They also have the ability to differentiate between short disturbances and permanent failures and modify their functionality accordingly. CAN nodes can transition from functioning like a normal node (being able to transmit and receive messages normally), to shutting down completely (Bus-Off) based on the severity of the errors detected. There are five error conditions (Section 3.4) and three error states (Section 3.5) defined in the CAN protocol that a node can be in, based upon the type and number of error conditions detected [21 – 22]. The errors simulated in this test are as follows: CRC Error, Acknowledge Error, Form Error, Bit Error, and Stuff Error. The error states simulated in this test are as follows: Error-Active, Error-Passive, and Bus-Off. CRC Error Test – For this test the Altera DE2 board is configured as the transmitting node while all 30 other nodes act as receivers. A 15-bit CRC value is calculated according to the following formula: 15 14 10 8 7 4 3 1 X X X X X X X . All other nodes on the network receive this message, calculate a CRC and verify that the CRC values match. For test purposes, bit 8 was complemented in the receiving nodes to cause 185
an Error Frame to be generated. After ten bit time slots, the message is resent with the proper CRC value to simulate whether all nodes received the message properly. Acknowledge Error – For this test, the Altera DE2 board checks if the Acknowledge Bit (which it has sent as a recessive bit) contains a dominant bit. The purpose of this dominant bit is to acknowledge that at least one node correctly received the message. If this bit is recessive, then no node received the message properly and an Acknowledge Error will occur. Both scenarios, recessive and dominant states, are tested to ensure proper message reception by all CAN nodes. For the recessive state, an Acknowledge Error occurs and an Error Frame is generated. After ten bit time slots the original message is resent with a dominant bit in the Acknowledge Field to verify the successful retransmission of the message. Form Error – If any node detects a dominant bit in the End of Frame, Interframe Space, Acknowledge Delimiter or CRC Delimiter, the CAN protocol defines this to be a form violation and a Form Error is generated. For this test, a dominant bit is placed in each of the bit positions to cause a Form Error to be generated for each of these conditions. After waiting for ten bit times, the original message is then resent to all 30 CAN nodes verifying proper operation. Bit Error – This situation arises if a transmitter sends a dominant bit and detects a recessive bit, or if it sends a recessive bit and detects a dominant bit when monitoring the actual bus level and comparing it to the bit that it has just sent. If a Bit Error is detected, an Error Frame is generated. To verify this, the actual bit sent is complemented from the receiver nodes and after ten bit times the bit is sent again in its uncomplemented form. 186
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DESIGN OF A CUSTOM ASIC INCORPORATI
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ABSTRACT The vast majority of today
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LIST OF ABBREVIATIONS AND SYMBOLS A
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ISO International Organization for
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SI Serial In SO Serial Out SOF Star
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ACKNOWLEDGEMENTS I would like to ex
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2.4 Types of Devices...............
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4.3.5 Communication Speed Different
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5.3.21.1 Synchronization Test (test
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5.3 Resource Utilization...........
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LIST OF FIGURES 2.1 1 - Wire® Netw
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4.12 Read-Data Time Slot...........
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6.4 DS1996 Address Registers ......
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manufacturing process. Structured o
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describes the 1 - Wire® and CAN co
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2.2 1 - Wire® Overview The basis o
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All 1 - Wire® masters described in
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attachments, microcontroller with b
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Figure 2.3 Bidirectional port pin w
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2.3.3 Synthesizable 1 - Wire® Bus
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Figure 2.7 UART/RS232 Serial Port I
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hardware. Through control registers
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Table 2.2 1 - Wire® Bus Operations
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2.3.6 1 - Wire® Search Algorithm F
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detected. This ‘read two bits’
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in Figure 2.15. Alternatively, the
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of the bit, then write the desired
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2.4.2 Device Functions and Typical
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and development (R&D) investments b
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2.5 Network Types and Precedents As
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2.5.2 1 - Wire® Network Topologies
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2.5.3 1 - Wire® Network Limitation
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with a single selected slave. If an
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user group was founded in March of
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protocol on multiple media for maxi
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ecessive bit and the monitored stat
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specification: Start-Of-Frame, Arbi
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Cyclic Redundancy Check (CRC) Field
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Arbitration FieldThe Arbitration Fi
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SOF SOF Bit 28 Bit 27 Arbitration f
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Afterwards it starts transmitting s
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Figure 3.9 Structure of the Interfr
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error occurs, an Error Frame is gen
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Table 3.4 Error Flag Output Timing
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3.5.2 Error-Passive A node becomes
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where tNBT is the Nominal Bit Time
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Figure 3.12 Propagation Delay Betwe
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3.6.4 Synchronization t t t t (3.
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opposite value is inserted into the
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many systems, the bus length will b
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CHAPTER 4 THE CHALLENGES OF INTERFA
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In June 2004, Maxim Integrated Prod
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Wearable sensor technology is a new
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In traditional bus architectures, o
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Figure 4.3 Centralized arbiter with
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For the initial prototype design pr
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the ID of 31 transmits a ‘0’ (d
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Recently, a technique has been prop
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procedure, then the address claim p
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paradigms are prevalent in the desi
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systems possess a higher flexibilit
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fixed identifier and hence a fixed
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348sm Cm 47 8 smbit 11-bit hea
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est-case latency occurs when the bu
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to break the 1 - Wire® network int
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ow, is most critical for power deli
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computations have device-specific p
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Table 4.7 Example results with N 2
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4.3.5 Communication Speed Different
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anging” a port pin on a microproc
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From Figure 5.1, the block I/O pins
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5.2.2 Command Register In addition
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specifies the selected bit value to
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with i > m. This process is repeate
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Figure 5.6 Interrupt Register. OW_
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the INTR pin will be pulled high si
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master reset occurs. Table 5.2 show
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EN_FOW: Enable Force One Wire. Sett
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READ_ROM - Used to read the 64-bit
Page 159 and 160: 5.2.8.1 Single Search ROM (single_s
Page 161 and 162: 5.2.8.3 Scratchpad Memory (scratchp
Page 163 and 164: 5.2.8.4 Command Recognition (cmd_re
Page 165 and 166: TBF - The Transmit Buffer provides
Page 167 and 168: compensate for the propagation dela
Page 169 and 170: Figure 5.15 CAN Module memory map [
Page 171 and 172: ‘0’, fast speed mode will be us
Page 173 and 174: COMP-SEL: Comparator Select. When t
Page 175 and 176: Figure 5.18 CAN Status Register. B
Page 177 and 178: that buffer is given to the CPU and
Page 179 and 180: Acceptance Mask Registers (accepted
Page 181 and 182: SJW1, SJW0: Synchronization Jump Wi
Page 183 and 184: TSEG22 - TSEG10: Time Segment Bits.
Page 185 and 186: The transmit clock (ttxclk) is used
Page 187 and 188: 5.3.13 CAN Module Transmit Buffer I
Page 189 and 190: Figure 5.28 CAN Transmit Data Segme
Page 191 and 192: 5.3.20 CAN Node Overview As stated
Page 193 and 194: Read Digital InputsRead the value o
Page 195 and 196: the clock high time is either 5 µs
Page 197 and 198: Yes Perform A/D Conversion on AN0 W
Page 199 and 200: and GP2 and GP5 as outputs. With th
Page 201 and 202: external INT pin, and then branches
Page 203 and 204: Read MCP2515 Rx Buffer for Digital
Page 205 and 206: When a valid message is received, t
Page 207 and 208: Table 5.19 Resource Utilization. Re
Page 209: For this test, only one CAN node wa
Page 213 and 214: messages, acknowledge messages, or
Page 215 and 216: 5.3.21.4 Send Basic Frame Test (sen
Page 217 and 218: going from one node to 30 nodes (se
Page 219 and 220: Table 6.1 Resource Utilization. Rev
Page 221 and 222: 6.2.1 Test Verification and Overvie
Page 223 and 224: has read access to this register. T
Page 225 and 226: system configuration used for this
Page 227 and 228: or not depends on the number of rec
Page 229 and 230: 6.4. There are two receiving CAN no
Page 231 and 232: CHAPTER 7 CONCLUSIONS AND FUTURE WO
Page 233 and 234: a communication bus reset will occu
Page 235 and 236: For the synthesizable CAN Controlle
Page 237 and 238: additional CAN nodes were added to
Page 239 and 240: Fall-Through Stack A LOW level on t
Page 241 and 242: In conclusion, the prototype system
Page 243 and 244: REFERENCES [1] IBM ASIC Products Ap
Page 245 and 246: [22] “CAN - a brief tutorial for
Page 247 and 248: [44] Microchip MCP2515 - Stand-Alon
Page 249 and 250: [67] K. Tindell and A. Burns, “Gu
Page 251 and 252: [88] “Verilog - A Language Refere
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DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...

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