DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...

A transmitting node will not resynchronize due to propagation delays of its own
transmitted message. The receivers will synchronize normally.
If the absolute magnitude of the phase error is greater than the SJW, then the
appropriate phase segment will be adjusted by an amount equal to the SJW.
The synchronization test performs a hard synchronization by transitioning the rx line
from recessive to dominant (logic “1” to logic “0”) and then waits for ten bit times before
transitioning from dominant to recessive (logic “0” to logic “1”). Ten more bit times pass before
another transition occurs. This simulates a resynchronization on time. This test also simulates
early (two frames early) and late resynchronization (two frames and one frame late) before
finally performing another resynchronization on time. For this test, no physical CAN nodes
were connected to the Altera DE2 Development and Education Board. This test was performed
and verified using ModelSim to prove validity and integrity of the synthesizable CAN
Controller and Verilog® code modules.
5.3.21.2 Bus-Off Test (bus_off_test)
This test simulates a CAN node being in the Bus-Off state (See Figure 3.10). For this
to happen, a value of 256 is placed in the TEC, since receive errors cannot cause a CAN node
to go Bus-Off. While in this state, the CAN node cannot send or receive messages,
acknowledge messages, or transmit Error Frames of any kind. At the present, the only way for a
CAN node to leave this state is by a software reset.
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