DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...

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condition is detected, the PIC® MCU performs a re-initialization of the MCP2515 and then attempts to transmit the error message (ID = 0x3FF) with an error code of 0x12. After initiating a request to send for the error message, the PIC® MCU checks to ensure that the message was transmitted successfully. If it was successfully transmitted, the PIC® MCU sets an internal flag to indicate that a Bus-Off condition occurred and then resumes normal operation. If the error message fails to transmit correctly, of if the Bus-Off condition is detected a second time, the PIC® MCU automatically enters an Idle loop and remains there until a system Reset occurs via power-on. 5.3.21 Verification of CAN Module To verify the proper operation of the synthesizable CAN Controller, five test cases were executed: Synchronization (test_synchronization), Bus Off (bus_off_test), Error Test (error_test), Send Basic Frame Test (send_frame_basic), and Send Extended Frame Test (send_frame_extended). All tests were compiled and simulated using Altera Quartus II 9.1 (32- bit) and ModelSim Altera Starter Edition 6.6c software on a PC executing Windows XP Service Pack 3. All tests were performed extensively while trying to cover all possible combinations of data and I/O values for the CAN Controller. Only a few failures (most were attributed to the addition and removal of nodes while tests were being conducted) were observed for any of the five tests described below. The source code for all modules, testbench code, and simulation results are located on the DVD included with this work. Table 5.19 shows the FPGA resource utilization for the Altera DE2 Development and Education Board. 181
Table 5.19 Resource Utilization. Revision Name CAN_Controller Family Cyclone II Device EP2C35F672C6 Timing Models Final Met timing requirements Yes Total logic elements 1560 / 33,216 ( 1 % ) Total combinational functions 1462 / 33,216 ( 1 % ) Dedicated logic registers 625 / 33,216 ( < 1 % ) Total registers 625 Total pins 19 / 475 ( 4 % ) Total virtual pins 0 Total memory bits 832 / 483,840 ( 0 % ) Embedded Multiplier 9-bit element 0 / 70 ( 0 % ) Total PLLs 0 / 4 ( 0 % ) 5.3.21.1 Synchronization Test (test_synchronization) All nodes on a CAN bus must have the same NBT. Since the CAN protocol is an asynchronous serial bus with Non-Return to Zero (NRZ) bit coding; a clock is not encoded into each message. The receivers must synchronize to the transmitted data stream to insure messages are properly decoded. There are two methods used for achieving and maintaining synchronization: hard synchronization and re-synchronization (Sections 3.6.4 – 3.6.5). When synchronizing, there are five basic rules to follow to synchronize the receivers with the transmitted data: Only recessive-to-dominant edges will be used for synchronization. Only one synchronization within one bit time is allowed. An edge will be used for synchronization only if the value at the previous sample point differs from the bus value immediately after the edge. 182
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DESIGN OF A CUSTOM ASIC INCORPORATI
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ABSTRACT The vast majority of today
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LIST OF ABBREVIATIONS AND SYMBOLS A
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ISO International Organization for
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SI Serial In SO Serial Out SOF Star
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ACKNOWLEDGEMENTS I would like to ex
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2.4 Types of Devices...............
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4.3.5 Communication Speed Different
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5.3.21.1 Synchronization Test (test
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5.3 Resource Utilization...........
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LIST OF FIGURES 2.1 1 - Wire® Netw
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4.12 Read-Data Time Slot...........
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6.4 DS1996 Address Registers ......
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manufacturing process. Structured o
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describes the 1 - Wire® and CAN co
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2.2 1 - Wire® Overview The basis o
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All 1 - Wire® masters described in
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attachments, microcontroller with b
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Figure 2.3 Bidirectional port pin w
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2.3.3 Synthesizable 1 - Wire® Bus
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Figure 2.7 UART/RS232 Serial Port I
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hardware. Through control registers
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Table 2.2 1 - Wire® Bus Operations
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2.3.6 1 - Wire® Search Algorithm F
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detected. This ‘read two bits’
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in Figure 2.15. Alternatively, the
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of the bit, then write the desired
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2.4.2 Device Functions and Typical
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and development (R&D) investments b
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2.5 Network Types and Precedents As
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2.5.2 1 - Wire® Network Topologies
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2.5.3 1 - Wire® Network Limitation
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with a single selected slave. If an
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user group was founded in March of
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protocol on multiple media for maxi
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ecessive bit and the monitored stat
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specification: Start-Of-Frame, Arbi
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Cyclic Redundancy Check (CRC) Field
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Arbitration FieldThe Arbitration Fi
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SOF SOF Bit 28 Bit 27 Arbitration f
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Afterwards it starts transmitting s
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Figure 3.9 Structure of the Interfr
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error occurs, an Error Frame is gen
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Table 3.4 Error Flag Output Timing
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3.5.2 Error-Passive A node becomes
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where tNBT is the Nominal Bit Time
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Figure 3.12 Propagation Delay Betwe
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3.6.4 Synchronization t t t t (3.
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opposite value is inserted into the
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many systems, the bus length will b
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CHAPTER 4 THE CHALLENGES OF INTERFA
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In June 2004, Maxim Integrated Prod
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Wearable sensor technology is a new
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In traditional bus architectures, o
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Figure 4.3 Centralized arbiter with
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For the initial prototype design pr
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the ID of 31 transmits a ‘0’ (d
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Recently, a technique has been prop
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procedure, then the address claim p
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paradigms are prevalent in the desi
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systems possess a higher flexibilit
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fixed identifier and hence a fixed
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348sm Cm 47 8 smbit 11-bit hea
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est-case latency occurs when the bu
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to break the 1 - Wire® network int
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ow, is most critical for power deli
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computations have device-specific p
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Table 4.7 Example results with N 2
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4.3.5 Communication Speed Different
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anging” a port pin on a microproc
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From Figure 5.1, the block I/O pins
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5.2.2 Command Register In addition
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specifies the selected bit value to
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with i > m. This process is repeate
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Figure 5.6 Interrupt Register. OW_
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the INTR pin will be pulled high si
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master reset occurs. Table 5.2 show
Page 155 and 156: EN_FOW: Enable Force One Wire. Sett
Page 157 and 158: READ_ROM - Used to read the 64-bit
Page 159 and 160: 5.2.8.1 Single Search ROM (single_s
Page 161 and 162: 5.2.8.3 Scratchpad Memory (scratchp
Page 163 and 164: 5.2.8.4 Command Recognition (cmd_re
Page 165 and 166: TBF - The Transmit Buffer provides
Page 167 and 168: compensate for the propagation dela
Page 169 and 170: Figure 5.15 CAN Module memory map [
Page 171 and 172: ‘0’, fast speed mode will be us
Page 173 and 174: COMP-SEL: Comparator Select. When t
Page 175 and 176: Figure 5.18 CAN Status Register. B
Page 177 and 178: that buffer is given to the CPU and
Page 179 and 180: Acceptance Mask Registers (accepted
Page 181 and 182: SJW1, SJW0: Synchronization Jump Wi
Page 183 and 184: TSEG22 - TSEG10: Time Segment Bits.
Page 185 and 186: The transmit clock (ttxclk) is used
Page 187 and 188: 5.3.13 CAN Module Transmit Buffer I
Page 189 and 190: Figure 5.28 CAN Transmit Data Segme
Page 191 and 192: 5.3.20 CAN Node Overview As stated
Page 193 and 194: Read Digital InputsRead the value o
Page 195 and 196: the clock high time is either 5 µs
Page 197 and 198: Yes Perform A/D Conversion on AN0 W
Page 199 and 200: and GP2 and GP5 as outputs. With th
Page 201 and 202: external INT pin, and then branches
Page 203 and 204: Read MCP2515 Rx Buffer for Digital
Page 205: When a valid message is received, t
Page 209 and 210: For this test, only one CAN node wa
Page 211 and 212: an Error Frame to be generated. Aft
Page 213 and 214: messages, acknowledge messages, or
Page 215 and 216: 5.3.21.4 Send Basic Frame Test (sen
Page 217 and 218: going from one node to 30 nodes (se
Page 219 and 220: Table 6.1 Resource Utilization. Rev
Page 221 and 222: 6.2.1 Test Verification and Overvie
Page 223 and 224: has read access to this register. T
Page 225 and 226: system configuration used for this
Page 227 and 228: or not depends on the number of rec
Page 229 and 230: 6.4. There are two receiving CAN no
Page 231 and 232: CHAPTER 7 CONCLUSIONS AND FUTURE WO
Page 233 and 234: a communication bus reset will occu
Page 235 and 236: For the synthesizable CAN Controlle
Page 237 and 238: additional CAN nodes were added to
Page 239 and 240: Fall-Through Stack A LOW level on t
Page 241 and 242: In conclusion, the prototype system
Page 243 and 244: REFERENCES [1] IBM ASIC Products Ap
Page 245 and 246: [22] “CAN - a brief tutorial for
Page 247 and 248: [44] Microchip MCP2515 - Stand-Alon
Page 249 and 250: [67] K. Tindell and A. Burns, “Gu
Page 251 and 252: [88] “Verilog - A Language Refere
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