DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...
DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ... DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...
5.3.20.3 MCP2515 Initialization Before the system can communicate on the CAN bus, the MCP2515 must be properly configured. The configuration of the MCP2515 is accomplished by loading the various control registers with the desired values. The firmware is written to take advantage of the table read functionality of the PIC® MCU. The values for each register are stored at the top of the PIC® ROM memory. During the MCP2515 initialization, the values are sequentially read by the table read function and then written to the MCP2515, via the SPI interface. The CAN bit rate configuration is controlled by the CNF1, CNF2 and CNF3 registers. The MCP2515 for each CAN node is configured to operate at a bus rate of 125 kbps using the following parameters: 8 MHz oscillator Baud rate prescaler equivalent to divide-by-4 8 TQ per bit time Sync segment: 1 TQ Prop segment: 1 TQ Phase segment 1: 3 TQ Phase segment 2: 3 TQ Sync Jump Width: 1 TQ 5.3.20.4 Interrupt Service Routine When an interrupt occurs, the PIC® MCU begins executing the ISR routine. Figure 5.35 shows the flowchart for the ISR. The ISR first determines the source of the interrupt, Timer0 or 175
external INT pin, and then branches to the appropriate section of code to process the interrupt. Figures 5.36 and 5.37 show the program flow for the Timer0 and CAN message received through interrupts, respectively. Read MCP2515 CANINTF Register ___ Msg Rx INT? No CAN Bus Error? No Yes System Error ___ (Invalid INT) Yes Yes ISR ___ INT Pin Interrupt Occurred? CAN Msg Received System Error (CANErr) No 176 Timer0 Interrupt? Yes Timer0 Time-out No System Error ___ (Invalid INT) Figure 5.35 CAN Node Interrupt Service Routine Flowchart [47]. When the Timer0 interrupt occurs, as shown in Figure 5.3, the PIC® MCU initiates an A/D conversion on AN0 constantly polling the ADDONE bit until the conversion process is complete. Once the conversion is complete, the ADRES value is loaded into the MCP2515 Transmit Buffer 0, Data Byte 0, and an RTS command is issued for Buffer 0. The TMR0 register is then reloaded and the interrupt flag is cleared. The interrupts are then re-enabled by the execution of the RETIE command at the end of the Timer0 ISR (See Figure 5.36).
- Page 149 and 150: Figure 5.6 Interrupt Register. OW_
- Page 151 and 152: the INTR pin will be pulled high si
- Page 153 and 154: master reset occurs. Table 5.2 show
- Page 155 and 156: EN_FOW: Enable Force One Wire. Sett
- Page 157 and 158: READ_ROM - Used to read the 64-bit
- Page 159 and 160: 5.2.8.1 Single Search ROM (single_s
- Page 161 and 162: 5.2.8.3 Scratchpad Memory (scratchp
- Page 163 and 164: 5.2.8.4 Command Recognition (cmd_re
- Page 165 and 166: TBF - The Transmit Buffer provides
- Page 167 and 168: compensate for the propagation dela
- Page 169 and 170: Figure 5.15 CAN Module memory map [
- Page 171 and 172: ‘0’, fast speed mode will be us
- Page 173 and 174: COMP-SEL: Comparator Select. When t
- Page 175 and 176: Figure 5.18 CAN Status Register. B
- Page 177 and 178: that buffer is given to the CPU and
- Page 179 and 180: Acceptance Mask Registers (accepted
- Page 181 and 182: SJW1, SJW0: Synchronization Jump Wi
- Page 183 and 184: TSEG22 - TSEG10: Time Segment Bits.
- Page 185 and 186: The transmit clock (ttxclk) is used
- Page 187 and 188: 5.3.13 CAN Module Transmit Buffer I
- Page 189 and 190: Figure 5.28 CAN Transmit Data Segme
- Page 191 and 192: 5.3.20 CAN Node Overview As stated
- Page 193 and 194: Read Digital InputsRead the value o
- Page 195 and 196: the clock high time is either 5 µs
- Page 197 and 198: Yes Perform A/D Conversion on AN0 W
- Page 199: and GP2 and GP5 as outputs. With th
- Page 203 and 204: Read MCP2515 Rx Buffer for Digital
- Page 205 and 206: When a valid message is received, t
- Page 207 and 208: Table 5.19 Resource Utilization. Re
- Page 209 and 210: For this test, only one CAN node wa
- Page 211 and 212: an Error Frame to be generated. Aft
- Page 213 and 214: messages, acknowledge messages, or
- Page 215 and 216: 5.3.21.4 Send Basic Frame Test (sen
- Page 217 and 218: going from one node to 30 nodes (se
- Page 219 and 220: Table 6.1 Resource Utilization. Rev
- Page 221 and 222: 6.2.1 Test Verification and Overvie
- Page 223 and 224: has read access to this register. T
- Page 225 and 226: system configuration used for this
- Page 227 and 228: or not depends on the number of rec
- Page 229 and 230: 6.4. There are two receiving CAN no
- Page 231 and 232: CHAPTER 7 CONCLUSIONS AND FUTURE WO
- Page 233 and 234: a communication bus reset will occu
- Page 235 and 236: For the synthesizable CAN Controlle
- Page 237 and 238: additional CAN nodes were added to
- Page 239 and 240: Fall-Through Stack A LOW level on t
- Page 241 and 242: In conclusion, the prototype system
- Page 243 and 244: REFERENCES [1] IBM ASIC Products Ap
- Page 245 and 246: [22] “CAN - a brief tutorial for
- Page 247 and 248: [44] Microchip MCP2515 - Stand-Alon
- Page 249 and 250: [67] K. Tindell and A. Burns, “Gu
external INT pin, and then branches to the appropriate section of code to process the interrupt.<br />
Figures 5.36 and 5.37 show the program flow for the Timer0 and CAN message received<br />
through interrupts, respectively.<br />
Read MCP2515<br />
CANINTF Register<br />
___<br />
Msg Rx INT?<br />
No<br />
CAN Bus Error?<br />
No<br />
Yes<br />
System Error ___ (Invalid<br />
INT)<br />
Yes<br />
Yes<br />
ISR<br />
___<br />
INT Pin<br />
Interrupt<br />
Occurred?<br />
CAN Msg Received<br />
System Error (CANErr)<br />
No<br />
176<br />
Timer0<br />
Interrupt?<br />
Yes<br />
Timer0 Time-out<br />
No<br />
System Error ___ (Invalid<br />
INT)<br />
Figure 5.35 CAN Node Interrupt Service Routine Flowchart [47].<br />
When the Timer0 interrupt occurs, as shown in Figure 5.3, the PIC® MCU initiates an<br />
A/D conversion on AN0 constantly polling the ADDONE bit until the conversion process is<br />
complete. Once the conversion is complete, the ADRES value is loaded into the MCP2515<br />
Transmit Buffer 0, Data Byte 0, and an RTS command is issued for Buffer 0. The TMR0<br />
register is then reloaded and the interrupt flag is cleared. The interrupts are then re-enabled by<br />
the execution of the RETIE command at the end of the Timer0 ISR (See Figure 5.36).
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