DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...
DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ... DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...
6.3 FILHITx Bit Definitions ..............................................................................................................203 6.4 Test Results ..................................................................................................................................204 7.1 FIFO Buffer Memory Pin Names and Descriptions ....................................................................215 xix
LIST OF FIGURES 2.1 1 – Wire® Network .....................................................................................................................5 2.2 Typical 1 – Wire® Communication Flow ...................................................................................10 2.3 Bidirectional port pin with optional circuit for strong pullup (dashed lines) ..............................12 2.4 Unidirectional port pins with optional circuit for strong pullup (dashed lines) ...........................12 2.5 µC with Built-In 1 – Wire® Master & optional strong pullup circuit (dashed lines) ..................13 2.6 ASIC/FPGA with optional circuit for strong pullup (dashed lines) ............................................14 2.7 UART/RS232 Serial Port Interface .............................................................................................16 2.8 I 2 C interface with optional circuit for extra strong pullup (dashed lines)....................................17 2.9 1 – Wire® Master for a USB interface ........................................................................................17 2.10 Reset/Presence Detect Sequence ................................................................................................20 2.11 Write Zero Time Slot .................................................................................................................21 2.12 Write One/Read One Time Slot .................................................................................................21 2.13 Read Zero Time Slot ..................................................................................................................22 2.14 64 – Bit Unique ROM ‘Registration’ Number ..........................................................................23 2.15 1 – Wire® 8 – bit CRC ..............................................................................................................26 2.16 Linear Network Topology..........................................................................................................36 2.17 Stubbed Network Topology .......................................................................................................36 2.18 Star Network Topology..............................................................................................................37 3.1 Typical CAN Bus Network ......................................................................................................43 xx
- Page 1 and 2: DESIGN OF A CUSTOM ASIC INCORPORATI
- Page 3 and 4: ABSTRACT The vast majority of today
- Page 5 and 6: LIST OF ABBREVIATIONS AND SYMBOLS A
- Page 7 and 8: ISO International Organization for
- Page 9 and 10: SI Serial In SO Serial Out SOF Star
- Page 11 and 12: ACKNOWLEDGEMENTS I would like to ex
- Page 13 and 14: 2.4 Types of Devices...............
- Page 15 and 16: 4.3.5 Communication Speed Different
- Page 17 and 18: 5.3.21.1 Synchronization Test (test
- Page 19: 5.3 Resource Utilization...........
- Page 23 and 24: 4.12 Read-Data Time Slot...........
- Page 25 and 26: 6.4 DS1996 Address Registers ......
- Page 27 and 28: manufacturing process. Structured o
- Page 29 and 30: describes the 1 - Wire® and CAN co
- Page 31 and 32: 2.2 1 - Wire® Overview The basis o
- Page 33 and 34: All 1 - Wire® masters described in
- Page 35 and 36: attachments, microcontroller with b
- Page 37 and 38: Figure 2.3 Bidirectional port pin w
- Page 39 and 40: 2.3.3 Synthesizable 1 - Wire® Bus
- Page 41 and 42: Figure 2.7 UART/RS232 Serial Port I
- Page 43 and 44: hardware. Through control registers
- Page 45 and 46: Table 2.2 1 - Wire® Bus Operations
- Page 47 and 48: 2.3.6 1 - Wire® Search Algorithm F
- Page 49 and 50: detected. This ‘read two bits’
- Page 51 and 52: in Figure 2.15. Alternatively, the
- Page 53 and 54: of the bit, then write the desired
- Page 55 and 56: 2.4.2 Device Functions and Typical
- Page 57 and 58: and development (R&D) investments b
- Page 59 and 60: 2.5 Network Types and Precedents As
- Page 61 and 62: 2.5.2 1 - Wire® Network Topologies
- Page 63 and 64: 2.5.3 1 - Wire® Network Limitation
- Page 65 and 66: with a single selected slave. If an
- Page 67 and 68: user group was founded in March of
- Page 69 and 70: protocol on multiple media for maxi
6.3 FILHITx Bit Definitions ..............................................................................................................203<br />
6.4 Test Results ..................................................................................................................................204<br />
7.1 FIFO Buffer Memory Pin Names and Descriptions ....................................................................215<br />
xix
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