DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...

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Table 5.18 CAN Node Message Identifiers. ID Tx/Rx Description 3F0 Rx Read Analog Channel 1 3F1 Rx Read Digital Inputs 3F2 Rx Change Digital Output 1 3F3 Rx Change Digital Output 2 3F4 Rx Change Unit Address 3F5 Rx Turn Off Outputs 3F8 Tx Analog Channel 1 Value 3F9 Tx Current Values of Digital Inputs 3FA Tx 3F2 Command Acknowledgement 3FB Tx 3F3 Command Acknowledgement 3FC Tx 3F4 Command Acknowledgement 3FD Tx 3F5 Command Acknowledgement 3FE Tx Analog Channel 0 Value 3FF Tx System Error The PIC12CE674 only has six available I/O pins, and all of these are used, two for analog inputs and four (three SPIs and one INT ) to interface to the MCP2515. This requires the system to take advantage of the internal RC oscillator of the PIC12CE674. The internal RC oscillator provides a 4 MHz system clock to the microcontroller, which translates to a 1 µs instruction cycle. The instruction cycle time directly affects the achievable speed of the SPI bus. This, in turn, determines the interrupt latency time as the SPI communication makes up the majority of the time required for the Interrupt Service Routine (ISR). The standard SPI interface has been modified in this application to use a common signal line for both Serial In (SI) and Serial Out (SO) lines, isolated from each other via a resistor. This method requires only three I/O pins to implement the SPI interface, instead of the usual four. Using this configuration does not support the Full-Duplex mode of SPI communications, which is not an issue in this application. The system achieves an overall SPI bus rate of slightly more than 80 kbps. The raw SPI clock rate averages 95 kbps. The clock low time is a fixed 5 µs, and 169
the clock high time is either 5 µs or 6 µs, depending upon whether a ‘0’ or a ‘1’ is being sent/received, which gives a worst case (sending the value 0xFF) raw clock rate of 90.0 kbps [47]. The overall effective speed achieved includes the additional software overhead of ‘bit- banging’ the SPI protocol. There are two interrupt sources in this CAN node system. The first is the PIC12CE674 Timer0 interrupt. This interrupt occurs approximately every 500 ms. The second interrupt source is the INT pin of the PIC12CE674. This pin is connected to the INT output of the MCP2515. This interrupt occurs any time a valid message is received or if the MCP2515 detects a CAN bus related error. This external interrupt is completely asynchronous with respect to the rest of the system. It is necessary to carefully consider the interrupt latency requirements during the system design/development phase. This CAN node system has two interrupt sources: the internal timer interrupt, which occurs approximately every 500 ms, and the external INT pin interrupt, which is generated by the MCP2515 CAN Controller and may occur at any time. The latency time for the timer ISR is essentially fixed. This parameter is a function of the time it takes for the ADC to perform a conversion on both channels, write the values to the transmit buffer, and issue a Request To Send (RTS) command to the MCP2515, via the SPI interface. This takes approximately 428 µs to complete. The MCP2515 has three pins that are configured as general purpose inputs and two pins that are configured as digital outputs. The inputs for each CAN node system are connected to switch contacts and the outputs are connected to LED indicators. The MCP2515 inputs have internal pull-up resistors and will read high when the attached switch is open and low when it is 170
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DESIGN OF A CUSTOM ASIC INCORPORATI
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ABSTRACT The vast majority of today
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LIST OF ABBREVIATIONS AND SYMBOLS A
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ISO International Organization for
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SI Serial In SO Serial Out SOF Star
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ACKNOWLEDGEMENTS I would like to ex
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2.4 Types of Devices...............
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4.3.5 Communication Speed Different
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5.3.21.1 Synchronization Test (test
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5.3 Resource Utilization...........
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LIST OF FIGURES 2.1 1 - Wire® Netw
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4.12 Read-Data Time Slot...........
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6.4 DS1996 Address Registers ......
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manufacturing process. Structured o
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describes the 1 - Wire® and CAN co
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2.2 1 - Wire® Overview The basis o
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All 1 - Wire® masters described in
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attachments, microcontroller with b
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Figure 2.3 Bidirectional port pin w
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2.3.3 Synthesizable 1 - Wire® Bus
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Figure 2.7 UART/RS232 Serial Port I
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hardware. Through control registers
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Table 2.2 1 - Wire® Bus Operations
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2.3.6 1 - Wire® Search Algorithm F
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detected. This ‘read two bits’
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in Figure 2.15. Alternatively, the
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of the bit, then write the desired
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2.4.2 Device Functions and Typical
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and development (R&D) investments b
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2.5 Network Types and Precedents As
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2.5.2 1 - Wire® Network Topologies
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2.5.3 1 - Wire® Network Limitation
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with a single selected slave. If an
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user group was founded in March of
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protocol on multiple media for maxi
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ecessive bit and the monitored stat
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specification: Start-Of-Frame, Arbi
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Cyclic Redundancy Check (CRC) Field
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Arbitration FieldThe Arbitration Fi
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SOF SOF Bit 28 Bit 27 Arbitration f
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Afterwards it starts transmitting s
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Figure 3.9 Structure of the Interfr
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error occurs, an Error Frame is gen
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Table 3.4 Error Flag Output Timing
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3.5.2 Error-Passive A node becomes
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where tNBT is the Nominal Bit Time
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Figure 3.12 Propagation Delay Betwe
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3.6.4 Synchronization t t t t (3.
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opposite value is inserted into the
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many systems, the bus length will b
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CHAPTER 4 THE CHALLENGES OF INTERFA
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In June 2004, Maxim Integrated Prod
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Wearable sensor technology is a new
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In traditional bus architectures, o
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Figure 4.3 Centralized arbiter with
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For the initial prototype design pr
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the ID of 31 transmits a ‘0’ (d
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Recently, a technique has been prop
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procedure, then the address claim p
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paradigms are prevalent in the desi
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systems possess a higher flexibilit
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fixed identifier and hence a fixed
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348sm Cm 47 8 smbit 11-bit hea
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est-case latency occurs when the bu
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to break the 1 - Wire® network int
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ow, is most critical for power deli
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computations have device-specific p
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Table 4.7 Example results with N 2
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4.3.5 Communication Speed Different
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anging” a port pin on a microproc
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From Figure 5.1, the block I/O pins
Page 143 and 144: 5.2.2 Command Register In addition
Page 145 and 146: specifies the selected bit value to
Page 147 and 148: with i > m. This process is repeate
Page 149 and 150: Figure 5.6 Interrupt Register. OW_
Page 151 and 152: the INTR pin will be pulled high si
Page 153 and 154: master reset occurs. Table 5.2 show
Page 155 and 156: EN_FOW: Enable Force One Wire. Sett
Page 157 and 158: READ_ROM - Used to read the 64-bit
Page 159 and 160: 5.2.8.1 Single Search ROM (single_s
Page 161 and 162: 5.2.8.3 Scratchpad Memory (scratchp
Page 163 and 164: 5.2.8.4 Command Recognition (cmd_re
Page 165 and 166: TBF - The Transmit Buffer provides
Page 167 and 168: compensate for the propagation dela
Page 169 and 170: Figure 5.15 CAN Module memory map [
Page 171 and 172: ‘0’, fast speed mode will be us
Page 173 and 174: COMP-SEL: Comparator Select. When t
Page 175 and 176: Figure 5.18 CAN Status Register. B
Page 177 and 178: that buffer is given to the CPU and
Page 179 and 180: Acceptance Mask Registers (accepted
Page 181 and 182: SJW1, SJW0: Synchronization Jump Wi
Page 183 and 184: TSEG22 - TSEG10: Time Segment Bits.
Page 185 and 186: The transmit clock (ttxclk) is used
Page 187 and 188: 5.3.13 CAN Module Transmit Buffer I
Page 189 and 190: Figure 5.28 CAN Transmit Data Segme
Page 191 and 192: 5.3.20 CAN Node Overview As stated
Page 193: Read Digital InputsRead the value o
Page 197 and 198: Yes Perform A/D Conversion on AN0 W
Page 199 and 200: and GP2 and GP5 as outputs. With th
Page 201 and 202: external INT pin, and then branches
Page 203 and 204: Read MCP2515 Rx Buffer for Digital
Page 205 and 206: When a valid message is received, t
Page 207 and 208: Table 5.19 Resource Utilization. Re
Page 209 and 210: For this test, only one CAN node wa
Page 211 and 212: an Error Frame to be generated. Aft
Page 213 and 214: messages, acknowledge messages, or
Page 215 and 216: 5.3.21.4 Send Basic Frame Test (sen
Page 217 and 218: going from one node to 30 nodes (se
Page 219 and 220: Table 6.1 Resource Utilization. Rev
Page 221 and 222: 6.2.1 Test Verification and Overvie
Page 223 and 224: has read access to this register. T
Page 225 and 226: system configuration used for this
Page 227 and 228: or not depends on the number of rec
Page 229 and 230: 6.4. There are two receiving CAN no
Page 231 and 232: CHAPTER 7 CONCLUSIONS AND FUTURE WO
Page 233 and 234: a communication bus reset will occu
Page 235 and 236: For the synthesizable CAN Controlle
Page 237 and 238: additional CAN nodes were added to
Page 239 and 240: Fall-Through Stack A LOW level on t
Page 241 and 242: In conclusion, the prototype system
Page 243 and 244: REFERENCES [1] IBM ASIC Products Ap
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[22] “CAN - a brief tutorial for
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[44] Microchip MCP2515 - Stand-Alon
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[67] K. Tindell and A. Burns, “Gu
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[88] “Verilog - A Language Refere
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