DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...

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ID2 – ID0: Identifier Bits. These bits contain the three least significant bits of the Transmit Buffer Identifier (TBI). RTR: Remote Transmission Request. When set to a ‘1’, a remote frame will be transmitted. When set to a ‘0’, a data frame will be transmitted. DLC3 – DLC0: Data Length Code Bits. The Data Length Code contains the number of bytes (data byte count) of the respective message. Upon transmission of a remote frame, the Data Length Code is ignored, forcing the number of bytes to be zero. The data byte count ranges from 0 – 8 for a data frame. Table 5.16 shows the effect of setting the DLC bits. Table 5.16 Data Length Code Bits. Data Length Code Bits Data Byte DLC3 DLC2 DLC1 DLC0 Count 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 8 5.3.15 CAN Module Transmit Data Segment Registers (TDS) 1 – 8 Depending upon the Data Length Code there may be up to eight data bytes transmitted as part of a data frame. Figure 5.28 shows the register bit definitions for the Transmit Data Segment Registers (TDS). 163
Figure 5.28 CAN Transmit Data Segment Registers. DB7 – DB0: Data Bits. These data bits in the eight data segment registers make up the bytes of data to be transmitted. The number of bytes to be transmitted is determined by the Data Length Code bits (bits 3 – 0) as defined in the TRTDL Register (See Section 5.3.14). 5.3.16 CAN Module Receive Buffer Registers Overview There are two full Receive Buffers (each ten bytes in length) used to handle all incoming messages being passed from the BSP to the CPU. Each Receive Buffer is capable of storing an entire message and has a layout identical to that of the Transmit Buffer. They are arranged in a double buffered configuration, with each buffer occupying the same area of the memory map. When the first buffer is filled it can be read by the CPU as a second incoming message is being transferred by the BSP into the second buffer. After the CPU has read a message from the Receive Buffer it can release that buffer, making it available for storing the next incoming message and allowing the second buffer to be read once it contains a complete message. The layout of these registers is shown in Table 5.17. Table 5.17 Receive Buffer Registers. Register Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Identifier (RBI) 30h ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 RTR/DLC (RRTDL) 31h ID2 ID1 ID0 RTR DLC3 DLC2 DLC1 DLC0 DSB1 (RDS1) 32h DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DSB2 (RDS2) 33h DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DSB3 (RDS3) 34h DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DSB4 (RDS4) 35h DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DSB5 (RDS5) 36h DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DSB6 (RDS6) 37h DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DSB7 (RDS7) 38h DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DSB8 (RDS8) 39h DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 164
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DESIGN OF A CUSTOM ASIC INCORPORATI
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ABSTRACT The vast majority of today
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LIST OF ABBREVIATIONS AND SYMBOLS A
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ISO International Organization for
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SI Serial In SO Serial Out SOF Star
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ACKNOWLEDGEMENTS I would like to ex
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2.4 Types of Devices...............
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4.3.5 Communication Speed Different
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5.3.21.1 Synchronization Test (test
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5.3 Resource Utilization...........
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LIST OF FIGURES 2.1 1 - Wire® Netw
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4.12 Read-Data Time Slot...........
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6.4 DS1996 Address Registers ......
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manufacturing process. Structured o
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describes the 1 - Wire® and CAN co
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2.2 1 - Wire® Overview The basis o
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All 1 - Wire® masters described in
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attachments, microcontroller with b
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Figure 2.3 Bidirectional port pin w
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2.3.3 Synthesizable 1 - Wire® Bus
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Figure 2.7 UART/RS232 Serial Port I
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hardware. Through control registers
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Table 2.2 1 - Wire® Bus Operations
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2.3.6 1 - Wire® Search Algorithm F
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detected. This ‘read two bits’
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in Figure 2.15. Alternatively, the
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of the bit, then write the desired
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2.4.2 Device Functions and Typical
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and development (R&D) investments b
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2.5 Network Types and Precedents As
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2.5.2 1 - Wire® Network Topologies
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2.5.3 1 - Wire® Network Limitation
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with a single selected slave. If an
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user group was founded in March of
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protocol on multiple media for maxi
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ecessive bit and the monitored stat
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specification: Start-Of-Frame, Arbi
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Cyclic Redundancy Check (CRC) Field
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Arbitration FieldThe Arbitration Fi
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SOF SOF Bit 28 Bit 27 Arbitration f
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Afterwards it starts transmitting s
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Figure 3.9 Structure of the Interfr
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error occurs, an Error Frame is gen
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Table 3.4 Error Flag Output Timing
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3.5.2 Error-Passive A node becomes
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where tNBT is the Nominal Bit Time
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Figure 3.12 Propagation Delay Betwe
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3.6.4 Synchronization t t t t (3.
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opposite value is inserted into the
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many systems, the bus length will b
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CHAPTER 4 THE CHALLENGES OF INTERFA
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In June 2004, Maxim Integrated Prod
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Wearable sensor technology is a new
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In traditional bus architectures, o
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Figure 4.3 Centralized arbiter with
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For the initial prototype design pr
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the ID of 31 transmits a ‘0’ (d
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Recently, a technique has been prop
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procedure, then the address claim p
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paradigms are prevalent in the desi
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systems possess a higher flexibilit
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fixed identifier and hence a fixed
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348sm Cm 47 8 smbit 11-bit hea
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est-case latency occurs when the bu
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to break the 1 - Wire® network int
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ow, is most critical for power deli
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computations have device-specific p
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Table 4.7 Example results with N 2
Page 137 and 138: 4.3.5 Communication Speed Different
Page 139 and 140: anging” a port pin on a microproc
Page 141 and 142: From Figure 5.1, the block I/O pins
Page 143 and 144: 5.2.2 Command Register In addition
Page 145 and 146: specifies the selected bit value to
Page 147 and 148: with i > m. This process is repeate
Page 149 and 150: Figure 5.6 Interrupt Register. OW_
Page 151 and 152: the INTR pin will be pulled high si
Page 153 and 154: master reset occurs. Table 5.2 show
Page 155 and 156: EN_FOW: Enable Force One Wire. Sett
Page 157 and 158: READ_ROM - Used to read the 64-bit
Page 159 and 160: 5.2.8.1 Single Search ROM (single_s
Page 161 and 162: 5.2.8.3 Scratchpad Memory (scratchp
Page 163 and 164: 5.2.8.4 Command Recognition (cmd_re
Page 165 and 166: TBF - The Transmit Buffer provides
Page 167 and 168: compensate for the propagation dela
Page 169 and 170: Figure 5.15 CAN Module memory map [
Page 171 and 172: ‘0’, fast speed mode will be us
Page 173 and 174: COMP-SEL: Comparator Select. When t
Page 175 and 176: Figure 5.18 CAN Status Register. B
Page 177 and 178: that buffer is given to the CPU and
Page 179 and 180: Acceptance Mask Registers (accepted
Page 181 and 182: SJW1, SJW0: Synchronization Jump Wi
Page 183 and 184: TSEG22 - TSEG10: Time Segment Bits.
Page 185 and 186: The transmit clock (ttxclk) is used
Page 187: 5.3.13 CAN Module Transmit Buffer I
Page 191 and 192: 5.3.20 CAN Node Overview As stated
Page 193 and 194: Read Digital InputsRead the value o
Page 195 and 196: the clock high time is either 5 µs
Page 197 and 198: Yes Perform A/D Conversion on AN0 W
Page 199 and 200: and GP2 and GP5 as outputs. With th
Page 201 and 202: external INT pin, and then branches
Page 203 and 204: Read MCP2515 Rx Buffer for Digital
Page 205 and 206: When a valid message is received, t
Page 207 and 208: Table 5.19 Resource Utilization. Re
Page 209 and 210: For this test, only one CAN node wa
Page 211 and 212: an Error Frame to be generated. Aft
Page 213 and 214: messages, acknowledge messages, or
Page 215 and 216: 5.3.21.4 Send Basic Frame Test (sen
Page 217 and 218: going from one node to 30 nodes (se
Page 219 and 220: Table 6.1 Resource Utilization. Rev
Page 221 and 222: 6.2.1 Test Verification and Overvie
Page 223 and 224: has read access to this register. T
Page 225 and 226: system configuration used for this
Page 227 and 228: or not depends on the number of rec
Page 229 and 230: 6.4. There are two receiving CAN no
Page 231 and 232: CHAPTER 7 CONCLUSIONS AND FUTURE WO
Page 233 and 234: a communication bus reset will occu
Page 235 and 236: For the synthesizable CAN Controlle
Page 237 and 238: additional CAN nodes were added to
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Fall-Through Stack A LOW level on t
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In conclusion, the prototype system
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REFERENCES [1] IBM ASIC Products Ap
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[22] “CAN - a brief tutorial for
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[44] Microchip MCP2515 - Stand-Alon
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[67] K. Tindell and A. Burns, “Gu
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[88] “Verilog - A Language Refere
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