DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...
DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ... DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...
Table 5.13 Output Control Bits. Bit Name Description OCTP0/1 These two bits control whether the P-type output control transistors are enabled. OCTN0/1 These two bits control whether the N-type output control transistors are enabled. OCPOL0/1 These two bits determine the driver output polarity for each of the CAN bus lines (TX0, TX1). TP0/1 These are the resulting states of the output transistors. TD This is the internal value of the data bit to be transferred across the CAN bus. (A zero corresponds to a dominant bit, a one to a recessive.) The actions of these bits in the Output Control Register are summarized in Table 5.14. Table 5.14 CAN driver output levels [95]. Mode TD OCPOLi OCTPi OCTNi TPi TNi TXi Output Level Float Pull-down Pull-up Push-pull 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 161 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Off Off Off Off Off Off Off Off Off On On Off Off On On Off 5.3.12 CAN Module Transmit Buffer Registers Overview Off Off Off Off On Off Off On Off Off Off Off On Off Off On Float Float Float Float Low Float Float Low Float High High Float Low High High Low The Transmit Buffer acts as interface between the CPU and the Bit Stream Processor (BSP). It is ten bytes long and is capable of storing a complete message plus message identifier. The layout of these registers is shown in Table 5.15. Table 5.15 Transmit Buffer Registers. Register Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Identifier (TBI) 20h ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 RTR/DLC (TRTDL) 21h ID2 ID1 ID0 RTR DLC3 DLC2 DLC1 DLC0 DSB1 (TDS1) 22h DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DSB2 (TDS2) 23h DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DSB3 (TDS3) 24h DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DSB4 (TDS4) 25h DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DSB5 (TDS5) 26h DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DSB6 (TDS6) 27h DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DSB7 (TDS7) 28h DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DSB8 (TDS8) 29h DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
5.3.13 CAN Module Transmit Buffer Identifier Register (TBI) The message ID’s must be unique on a CAN bus, otherwise two nodes would continue transmission beyond the end of the arbitration field (ID), causing an error. Figure 5.26 shows the CAN Transmit Buffer Identifier Register (TBI). Figure 5.26 CAN Transmit Buffer Identifier Register. ID10 – ID3: Identifier Bits. The identifier consists of 11 bits (ID10 – ID0). ID10 is the most significant bit and is transmitted first on the bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. The three least significant bits are contained in the TRTDL register (See Section 5.3.14). The seven most significant bits must not all be recessive. 5.3.14 CAN Module Remote Transmission Request/Data Length Code Register (TRTDL) The Remote Transmission Request and Data Length Code Register, shown in Figure 5.27, contains the bits responsible for setting the number of bytes or data byte count of the respective CAN message and dictating to the CAN bus whether a remote frame or a data frame will be transmitted. Figure 5.27 CAN Remote Transmission Request/Data Length Code Register. 162
- Page 135 and 136: Table 4.7 Example results with N 2
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- Page 141 and 142: From Figure 5.1, the block I/O pins
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- Page 147 and 148: with i > m. This process is repeate
- Page 149 and 150: Figure 5.6 Interrupt Register. OW_
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- Page 153 and 154: master reset occurs. Table 5.2 show
- Page 155 and 156: EN_FOW: Enable Force One Wire. Sett
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- Page 159 and 160: 5.2.8.1 Single Search ROM (single_s
- Page 161 and 162: 5.2.8.3 Scratchpad Memory (scratchp
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- Page 165 and 166: TBF - The Transmit Buffer provides
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- Page 181 and 182: SJW1, SJW0: Synchronization Jump Wi
- Page 183 and 184: TSEG22 - TSEG10: Time Segment Bits.
- Page 185: The transmit clock (ttxclk) is used
- Page 189 and 190: Figure 5.28 CAN Transmit Data Segme
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- Page 203 and 204: Read MCP2515 Rx Buffer for Digital
- Page 205 and 206: When a valid message is received, t
- Page 207 and 208: Table 5.19 Resource Utilization. Re
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- Page 215 and 216: 5.3.21.4 Send Basic Frame Test (sen
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5.3.13 CAN Module Transmit Buffer Identifier Register (TBI)<br />
The message ID’s must be unique on a CAN bus, otherwise two nodes would continue<br />
transmission beyond the end of the arbitration field (ID), causing an error. Figure 5.26 shows the<br />
CAN Transmit Buffer Identifier Register (TBI).<br />
Figure 5.26 CAN Transmit Buffer Identifier Register.<br />
ID10 – ID3: Identifier Bits. The identifier consists of 11 bits (ID10 – ID0). ID10 is the<br />
most significant bit and is transmitted first on the bus during the arbitration procedure.<br />
The priority of an identifier is defined to be highest for the smallest binary number. The<br />
three least significant bits are contained in the TRTDL register (See Section 5.3.14). The<br />
seven most significant bits must not all be recessive.<br />
5.3.14 CAN Module Remote Transmission Request/Data Length Code Register (TRTDL)<br />
The Remote Transmission Request and Data Length Code Register, shown in Figure<br />
5.27, contains the bits responsible for setting the number of bytes or data byte count of the<br />
respective CAN message and dictating to the CAN bus whether a remote frame or a data<br />
frame will be transmitted.<br />
Figure 5.27 CAN Remote Transmission Request/Data Length Code Register.<br />
162
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