DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...
DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...
DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...
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Table 5.13 Output Control Bits.<br />
Bit Name Description<br />
OCTP0/1 These two bits control whether the P-type output control transistors are enabled.<br />
OCTN0/1 These two bits control whether the N-type output control transistors are enabled.<br />
OCPOL0/1 These two bits determine the driver output polarity for each of the CAN bus lines (TX0, TX1).<br />
TP0/1 These are the resulting states of the output transistors.<br />
TD<br />
This is the internal value of the data bit to be transferred across the CAN bus.<br />
(A zero corresponds to a dominant bit, a one to a recessive.)<br />
The actions of these bits in the Output Control Register are summarized in Table 5.14.<br />
Table 5.14 CAN driver output levels [95].<br />
Mode TD OCPOLi OCTPi OCTNi TPi TNi TXi Output Level<br />
Float<br />
Pull-down<br />
Pull-up<br />
Push-pull<br />
0<br />
1<br />
0<br />
1<br />
0<br />
1<br />
0<br />
1<br />
0<br />
1<br />
0<br />
1<br />
0<br />
1<br />
0<br />
1<br />
0<br />
0<br />
1<br />
1<br />
0<br />
0<br />
1<br />
1<br />
0<br />
0<br />
1<br />
1<br />
0<br />
0<br />
1<br />
1<br />
0<br />
0<br />
0<br />
0<br />
0<br />
0<br />
0<br />
0<br />
1<br />
1<br />
1<br />
1<br />
1<br />
1<br />
1<br />
1<br />
161<br />
0<br />
0<br />
0<br />
0<br />
1<br />
1<br />
1<br />
1<br />
0<br />
0<br />
0<br />
0<br />
1<br />
1<br />
1<br />
1<br />
Off<br />
Off<br />
Off<br />
Off<br />
Off<br />
Off<br />
Off<br />
Off<br />
Off<br />
On<br />
On<br />
Off<br />
Off<br />
On<br />
On<br />
Off<br />
5.3.12 CAN Module Transmit Buffer Registers Overview<br />
Off<br />
Off<br />
Off<br />
Off<br />
On<br />
Off<br />
Off<br />
On<br />
Off<br />
Off<br />
Off<br />
Off<br />
On<br />
Off<br />
Off<br />
On<br />
Float<br />
Float<br />
Float<br />
Float<br />
Low<br />
Float<br />
Float<br />
Low<br />
Float<br />
High<br />
High<br />
Float<br />
Low<br />
High<br />
High<br />
Low<br />
The Transmit Buffer acts as interface between the CPU and the Bit Stream Processor<br />
(BSP). It is ten bytes long and is capable of storing a complete message plus message identifier.<br />
The layout of these registers is shown in Table 5.15.<br />
Table 5.15 Transmit Buffer Registers.<br />
Register Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0<br />
Identifier (TBI) 20h ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3<br />
RTR/DLC (TRTDL) 21h ID2 ID1 ID0 RTR DLC3 DLC2 DLC1 DLC0<br />
DSB1 (TDS1) 22h DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0<br />
DSB2 (TDS2) 23h DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0<br />
DSB3 (TDS3) 24h DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0<br />
DSB4 (TDS4) 25h DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0<br />
DSB5 (TDS5) 26h DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0<br />
DSB6 (TDS6) 27h DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0<br />
DSB7 (TDS7) 28h DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0<br />
DSB8 (TDS8) 29h DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0