DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...

TSEG22 – TSEG10: Time Segment Bits. Time segments within the bit time fix the
number of clock cycles per bit time and the location of the sample point. Time Segment
TSEG1 and Time Segment TSEG2 are programmable as shown in Table 5.11.
Table 5.11 Time Segment Values.
TSEG13 TSEG12 TSEG11 TSEG10 Time Segment 1 TSEG22 TSEG21 TSEG20 Time Segment 2
0 0 0 1 2 tSCL cycles 0 0 1 2 tSCL cycles
0 0 1 0 3 tSCL cycles : : :
0 0 1 1 4 tSCL cycles : : :
: : : : : 1 1 1 8 tSCL cycles
: : : : :
1 1 1 1 16 tSCL cycles
The bit time is determined by the oscillator frequency, the baud rate prescaler, and the
number of bus clock cycles (tSCL) per bit. From Section 3.6.1, the bit time is calculated as shown
in Equation 5.1:
BIT _TIME SYNC _ SEG TSEG1 TSEG2
(5.1)
TSEG2 must be at least 2*tSCL, i.e. the configuration bits must not be 000. (If three samples per
bit mode is selected then TSEG2 must be at least 3*tSCL.) TSEG1 must be at least as long as
TSEG2. The Synchronization Jump Width (SJW) may not exceed TSEG2, and must be at least
tSCL shorter than TSEG1 to allow for physical propagation delays.
i.e. in terms of tSCL:
SYNC _SEG1 TSEG1SJW1 TSEG1TSEG2 TSEG2 SJW
and TSEG2 2 SAMP 0
or TSEG2 3 SAMP 1
These boundary conditions result in minimum bit times of 5*tSCL, for one sample per bit, and
7*tSCL, for three samples per bit.
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