DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...

of the corresponding bit in the Acceptance Code Register will not affect whether or not the
message is accepted.
Figure 5.21 CAN Acceptance Mask Register.
5.3.9 CAN Module Bus Timing Register 0 (CBT0)
The CAN Bus Timing Registers are used to select a suitable baud rate prescaler value
to provide an appropriate system clock cycle time (tSCL) value, which is then used to derive the
bit time and position of the sample point within the bit. Figure 3.11 (See Section 3.6.1) shows
the components of the CAN Bit Time Segments. The Bus Timing Registers allow the two
values, TSEG1 and TSEG2, to be defined. TSEG1 is the sum of PHASE_SEG1 and the
PROP_SEG (See Equation 3.4). TSEG2 is equal to PHASE_SEG2 (See Equation 3.5). The Bus
Timing Registers also define the size of the RESYNCHRONIZATION JUMP WIDTH (See
Section 3.6.5). This is the amount by which a bit can be lengthened or shortened during the
resynchronization process.
register is set.
Shown in Figure 5.22, this register can only be accessed when the RR bit in the CCNTRL
Figure 5.22 CAN Bus Timing Register 0.
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