DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...

LIST OF TABLES
2.1 Port Adapters for 1 – Wire® Devices ..........................................................................................18
2.2 1 – Wire® Bus Operations ...........................................................................................................20
2.3 1 – Wire® Bit Search Information ...............................................................................................23
2.4 1 – Wire® Master and Slave Search Sequence............................................................................24
2.5 1 – Wire® Search Path Direction ................................................................................................25
3.1 Frame Types and Roles of Each Frame .......................................................................................47
3.2 Data Length Code Field ...............................................................................................................49
3.3 Types of Errors ............................................................................................................................61
3.4 Error Flag Output Timing ............................................................................................................62
3.5 Types of Segments and Their Roles ............................................................................................68
4.1 Address claim status and reserved bits ........................................................................................90
4.2 Time-Triggered vs. Event-Triggered ...........................................................................................94
4.3 Categorization of Real-Time Systems .........................................................................................96
4.4 Time Savings for a Read ROM Function ....................................................................................103
4.5 Parameters of Impact ...................................................................................................................107
4.6 Results Matrix ..............................................................................................................................108
4.7 Example results with N 20 .......................................................................................................110
5.1 1 – Wire® Register Addresses .....................................................................................................116
5.2 Clock Divisor Register Settings for Input Clock Rates ...............................................................128
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