DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...

Acceptance Mask Registers (accepted); otherwise, the message will be overwritten by the next
message (dropped). Shown in Figure 5.20, this register can only be accessed when the RR bit in
the CCNTRL register is set.
Figure 5.20 CAN Acceptance Code Register.
AC7 – AC0: Acceptance Code Bits. These bits comprise a user defined sequence of bits
with which the 8 most significant bits of the message identifier (ID10 – ID3) are
compared. The result of this comparison is then masked with the Acceptance Mask
Register. Once a message has passed the acceptance criterion the respective identifier,
data length code and data are sequentially stored in a receive buffer, providing there is
one free. If there is no free buffer, the data overrun condition will be signaled. On
acceptance the receive buffer status bit is set to full and the receive interrupt bit is set
(provided RIE=enabled).
5.3.8 CAN Module Acceptance Mask Register (CACM)
The Acceptance Mask Register, shown in Figure 5.21, specifies which of the
corresponding bits in the Acceptance Code Register are relevant for acceptance filtering. This
register can only be accessed when the RR bit in the CCNTRL register is set. When a particular
bit in this register is clear, this indicates that the corresponding bit in the Acceptance Code
Register must be the same as its corresponding identifier bit, before a match will be detected.
The message will be accepted if all such bits match. When a bit is set, it indicates that the state
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