DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...

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Like all the bits in this register, EIF is cleared by reading the register, or by an external reset. TIF: Transmit Interrupt Flag. The TIF bit is set at the end of a transmission whenever both the TBA (bit 2 of CSTAT register) and TIE (bit 2 of CCNTRL register) bits are set. Like all the bits in this register, TIF is cleared by reading the register, or when reset request is set. RIF: Receive Interrupt Flag. The RIF bit is set by the CAN Module when a new message is available in the receive buffer, and the RIE bit in CCNTRL is set. At the same time the RBS bit in the CSTAT register also gets set, indicating a new message is available. Like all the bits in this register, RIF is cleared by reading the register, or when reset request is set. 5.3.7 CAN Module Acceptance Code Register (CACC) The Acceptance Code and Acceptance Mask Registers are used to provide limited message filtering on the eight most significant bits of the identifier. The Acceptance Mask Register defines which bits of the Acceptance Code Register are compared with the identifier of the incoming message. If the CAN Module receives a message with an identifier which does not meet its acceptance criterion, then it will respond by transmitting a dominant bit in the correct position of the ACK field, but will not transfer the message to the receive buffers or indicate to the CPU that a new message has been received [96]. On reception each message is written into the current receive buffer. The CPU is only signaled to read the message however, if it passes the criteria in the Acceptance Code and 153
Acceptance Mask Registers (accepted); otherwise, the message will be overwritten by the next message (dropped). Shown in Figure 5.20, this register can only be accessed when the RR bit in the CCNTRL register is set. Figure 5.20 CAN Acceptance Code Register. AC7 – AC0: Acceptance Code Bits. These bits comprise a user defined sequence of bits with which the 8 most significant bits of the message identifier (ID10 – ID3) are compared. The result of this comparison is then masked with the Acceptance Mask Register. Once a message has passed the acceptance criterion the respective identifier, data length code and data are sequentially stored in a receive buffer, providing there is one free. If there is no free buffer, the data overrun condition will be signaled. On acceptance the receive buffer status bit is set to full and the receive interrupt bit is set (provided RIE=enabled). 5.3.8 CAN Module Acceptance Mask Register (CACM) The Acceptance Mask Register, shown in Figure 5.21, specifies which of the corresponding bits in the Acceptance Code Register are relevant for acceptance filtering. This register can only be accessed when the RR bit in the CCNTRL register is set. When a particular bit in this register is clear, this indicates that the corresponding bit in the Acceptance Code Register must be the same as its corresponding identifier bit, before a match will be detected. The message will be accepted if all such bits match. When a bit is set, it indicates that the state 154
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DESIGN OF A CUSTOM ASIC INCORPORATI
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ABSTRACT The vast majority of today
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LIST OF ABBREVIATIONS AND SYMBOLS A
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ISO International Organization for
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SI Serial In SO Serial Out SOF Star
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ACKNOWLEDGEMENTS I would like to ex
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2.4 Types of Devices...............
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4.3.5 Communication Speed Different
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5.3.21.1 Synchronization Test (test
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5.3 Resource Utilization...........
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LIST OF FIGURES 2.1 1 - Wire® Netw
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4.12 Read-Data Time Slot...........
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6.4 DS1996 Address Registers ......
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manufacturing process. Structured o
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describes the 1 - Wire® and CAN co
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2.2 1 - Wire® Overview The basis o
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All 1 - Wire® masters described in
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attachments, microcontroller with b
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Figure 2.3 Bidirectional port pin w
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2.3.3 Synthesizable 1 - Wire® Bus
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Figure 2.7 UART/RS232 Serial Port I
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hardware. Through control registers
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Table 2.2 1 - Wire® Bus Operations
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2.3.6 1 - Wire® Search Algorithm F
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detected. This ‘read two bits’
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in Figure 2.15. Alternatively, the
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of the bit, then write the desired
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2.4.2 Device Functions and Typical
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and development (R&D) investments b
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2.5 Network Types and Precedents As
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2.5.2 1 - Wire® Network Topologies
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2.5.3 1 - Wire® Network Limitation
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with a single selected slave. If an
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user group was founded in March of
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protocol on multiple media for maxi
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ecessive bit and the monitored stat
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specification: Start-Of-Frame, Arbi
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Cyclic Redundancy Check (CRC) Field
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Arbitration FieldThe Arbitration Fi
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SOF SOF Bit 28 Bit 27 Arbitration f
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Afterwards it starts transmitting s
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Figure 3.9 Structure of the Interfr
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error occurs, an Error Frame is gen
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Table 3.4 Error Flag Output Timing
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3.5.2 Error-Passive A node becomes
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where tNBT is the Nominal Bit Time
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Figure 3.12 Propagation Delay Betwe
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3.6.4 Synchronization t t t t (3.
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opposite value is inserted into the
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many systems, the bus length will b
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CHAPTER 4 THE CHALLENGES OF INTERFA
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In June 2004, Maxim Integrated Prod
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Wearable sensor technology is a new
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In traditional bus architectures, o
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Figure 4.3 Centralized arbiter with
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For the initial prototype design pr
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the ID of 31 transmits a ‘0’ (d
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Recently, a technique has been prop
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procedure, then the address claim p
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paradigms are prevalent in the desi
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systems possess a higher flexibilit
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fixed identifier and hence a fixed
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348sm Cm 47 8 smbit 11-bit hea
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Page 131 and 132: ow, is most critical for power deli
Page 133 and 134: computations have device-specific p
Page 135 and 136: Table 4.7 Example results with N 2
Page 137 and 138: 4.3.5 Communication Speed Different
Page 139 and 140: anging” a port pin on a microproc
Page 141 and 142: From Figure 5.1, the block I/O pins
Page 143 and 144: 5.2.2 Command Register In addition
Page 145 and 146: specifies the selected bit value to
Page 147 and 148: with i > m. This process is repeate
Page 149 and 150: Figure 5.6 Interrupt Register. OW_
Page 151 and 152: the INTR pin will be pulled high si
Page 153 and 154: master reset occurs. Table 5.2 show
Page 155 and 156: EN_FOW: Enable Force One Wire. Sett
Page 157 and 158: READ_ROM - Used to read the 64-bit
Page 159 and 160: 5.2.8.1 Single Search ROM (single_s
Page 161 and 162: 5.2.8.3 Scratchpad Memory (scratchp
Page 163 and 164: 5.2.8.4 Command Recognition (cmd_re
Page 165 and 166: TBF - The Transmit Buffer provides
Page 167 and 168: compensate for the propagation dela
Page 169 and 170: Figure 5.15 CAN Module memory map [
Page 171 and 172: ‘0’, fast speed mode will be us
Page 173 and 174: COMP-SEL: Comparator Select. When t
Page 175 and 176: Figure 5.18 CAN Status Register. B
Page 177: that buffer is given to the CPU and
Page 181 and 182: SJW1, SJW0: Synchronization Jump Wi
Page 183 and 184: TSEG22 - TSEG10: Time Segment Bits.
Page 185 and 186: The transmit clock (ttxclk) is used
Page 187 and 188: 5.3.13 CAN Module Transmit Buffer I
Page 189 and 190: Figure 5.28 CAN Transmit Data Segme
Page 191 and 192: 5.3.20 CAN Node Overview As stated
Page 193 and 194: Read Digital InputsRead the value o
Page 195 and 196: the clock high time is either 5 µs
Page 197 and 198: Yes Perform A/D Conversion on AN0 W
Page 199 and 200: and GP2 and GP5 as outputs. With th
Page 201 and 202: external INT pin, and then branches
Page 203 and 204: Read MCP2515 Rx Buffer for Digital
Page 205 and 206: When a valid message is received, t
Page 207 and 208: Table 5.19 Resource Utilization. Re
Page 209 and 210: For this test, only one CAN node wa
Page 211 and 212: an Error Frame to be generated. Aft
Page 213 and 214: messages, acknowledge messages, or
Page 215 and 216: 5.3.21.4 Send Basic Frame Test (sen
Page 217 and 218: going from one node to 30 nodes (se
Page 219 and 220: Table 6.1 Resource Utilization. Rev
Page 221 and 222: 6.2.1 Test Verification and Overvie
Page 223 and 224: has read access to this register. T
Page 225 and 226: system configuration used for this
Page 227 and 228: or not depends on the number of rec
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6.4. There are two receiving CAN no
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CHAPTER 7 CONCLUSIONS AND FUTURE WO
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a communication bus reset will occu
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For the synthesizable CAN Controlle
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additional CAN nodes were added to
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Fall-Through Stack A LOW level on t
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In conclusion, the prototype system
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REFERENCES [1] IBM ASIC Products Ap
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[22] “CAN - a brief tutorial for
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[44] Microchip MCP2515 - Stand-Alon
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[67] K. Tindell and A. Burns, “Gu
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[88] “Verilog - A Language Refere
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