DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...

that buffer is given to the CPU and RBS is immediately set again. The first receive
buffer is then available for the next incoming message from the CAN Module.
5.3.6 CAN Module Interrupt Register (CINT)
The CAN Module has only one interrupt vector assigned to it. The Interrupt Register,
shown in Figure 5.19, can be read to determine the source of a CAN interrupt. The five
interrupt sources include: Wake Up, Data Overrun (a third message being received before either
of the Receive Buffers have been released), Error (either read or write error counter reaching a
pre-determined level), Transmission Complete, and Receive Interrupt [96]. All bits of this
register are read only; all are cleared by a read of this register. However, this register must be
read in the interrupt handling routine in order to enable further interrupts.
Figure 5.19 CAN Interrupt Register.
WIF: Wake-Up Interrupt Flag. If the CAN module detects bus activity while it is in
the SLEEP state, it clears the SLEEP in the CCOM register; the WIF bit will then be set.
WIF is cleared by reading the CAN Interrupt Register (CINT), or by an external reset.
OIF: Overrun Interrupt Flag. When OIE (bit 4 of CCNTRL register) is set this bit will
be set when a data overrun condition is detected. Like all the bits in this register, OIF is
cleared by reading the register, or when an external reset request is set.
EIF: Error Interrupt Flag. When EIE (bit 3 of CCNTRL register) is set then this bit will
be set by a change in the error or bus status bits in the CAN module status register.
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