DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...

when the RS bit (see CSTAT register – Section 5.3.5) becomes set. Setting this bit to a
‘0’ causes no action to be performed.
AT: Abort Transmission. When this bit is set to a ‘1’, a pending message transmission
will be cancelled if it is not already in progress. This allows the transmit buffer to be
loaded with a new, higher priority message when the buffer is released. If the CPU tries
to write to the buffer when it is locked, the information will be lost without being
signaled. The status register can be checked to see if transmission was aborted or is still
in progress. Setting this bit to a ‘0’ has no effect.
TR: Transmission Request. When this bit is set to a ‘1’, a data frame or a remote frame
will be transmitted depending on the transmission buffer’s contents. Setting this bit to a
‘0’ has no effect. It will not cancel a previously requested transmission; the abort
transmission request bit must be used to do this.
5.3.5 CAN Module Status Register (CSTAT)
The Status Register, shown in Figure 5.18, provides information on a number of
conditions which can occur in the CAN Module. This includes information on the status of
the last requested transmission, incoming messages and the availability of the Transmit Buffer
for acceptance of new messages for transmission. It also provides a flag to indicate the module
‘off bus’ state and provides limited information on the status of the error counters [96]. This
register is a read only register and only the CAN Module can change its contents.
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