DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...

BS (CAN Status Register (CSTAT) Bus Status bit) bit being set, the CAN Module
waits for 128 occurrences of 11 recessive bits before starting normal operation.
5.3.4 CAN Module Command Register (CCOM)
The Command Register, shown in Figure 5.17, is a write only register which contains the
Release Receive Buffer (RRB) and Transmit Request (TR) bits. Bits RX0, RX1, and COMP-
SEL are used to control the input comparator configuration, allowing it to operate correctly for
single-wire (not implemented yet) and differential modes of operation [96]. A read of this
register location will always return a value of $FF. This register may be written only when the
RR bit in CCNTRL is clear.
Figure 5.17 CAN Command Register.
RX0: Receive Pin 0. When this bit is set to a ‘1’, VDD/2 will be connected to the input
comparator. The RX0 pin is disconnected. When this bit is set to a ‘0’, the RX0 pin will
be connected to the input comparator. VDD/2 is then disconnected.
RX1: Receive Pin 1. Setting this bit to a ‘1’ will connect VDD/2 to the input comparator
and disconnect the RX1 pin. Setting this bit to a ‘0’ will connect the RX1 pin to the input
comparator and disconnect VDD/2. If, however, both RX0 and RX1 are set, or both are
clear, then neither of the RX pins will be disconnected.
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