DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...

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Table 5.8 Control Registers [95 – 96]. Register Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Control (CCNTRL) 10h X SPD X OIE EIE TIE RIE RR Command (CCOM) 11h RX0 RX1 COMP-SEL SLEEP COS RRB AT TR Status (CSTAT) 12h BS ES TS RS TCS TBA DO RBS Interrupt (CINT) 13h X X X WIF OIF EIF TIF RIF Acceptance code (CACC) 14h AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Acceptance mask (CACM) 15h AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Bus timing 0 (CBT0) 16h SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 Bus timing 1 (CBT1) 17h SAMP TSEG-22 TSEG-21 TSEG-20 TSEG-13 TSEG-12 TSEG-11 TSEG-10 Output Control (COCNTRL) 18h OCT-P1 OCT-N1 OCPOL1 OCT-P0 OCT-N0 OCPL0 OCM1 OCM0 Test Register 19h X X X X X X X X Note: The acceptance code register, acceptance mask register, bus timing register 0, bus timing register 1 and the output control register are only accessible when the RESET REQUEST (RR) bit in the CAN control register (CCNTRL) is set. It is not foreseen that these registers will be referenced again after the initial reset sequence [95]. 5.3.3 CAN Module Control Register (CCNTRL) The Control Register, shown in Figure 5.16, provides the local mask bits for the CAN Module interrupts. In addition, it contains the Reset Request (RR) bit, which is set to disable the CAN Module operation and allow access to the message filtering, bus timing and output control registers [96]. This register may be read or written by the microprocessor; only the RR bit is affected by the CAN Module. Figure 5.16 CAN Control Register. SPD: Speed Mode. When this bit is set to ‘1’, slow speed mode will be used for resynchronization. Bus line transitions from both recessive to dominant and from dominant to recessive will be used for resynchronization. When this bit is cleared, set to 145
‘0’, fast speed mode will be used for resynchronization. Only transitions from recessive to dominant will be used for resynchronization. OIE: Overrun Interrupt Enable. Setting this bit to a ‘1’ enables the CPU to get an interrupt request whenever the Overrun Status bit gets set. Setting this bit to a ‘0’ will prevent the CPU from getting an overrun interrupt request. EIE: Error Interrupt Enable. Setting this bit to a ‘1’ enables the CPU to get an interrupt request whenever the error status or bus status bits in the CSTAT register change. Setting this bit to a ‘0’ disables the CPU from receiving error interrupt requests. TIE: Transmit Interrupt Enable. If enabled (set to a ‘1’), the CPU will get an interrupt request whenever a message has been successfully transmitted, or when the transmit buffer is accessible again following an ABORT command. If disabled (set to a ‘0’), the CPU will not get a transmit interrupt request. RIE: Receive Interrupt Enable. Setting this bit to a ‘1’ will enable the CPU to get an interrupt request whenever a message has been received free of errors. If set to a ‘0’, the CPU will not get a receive interrupt request. RR: Reset Request. If the RR bit is set, the CAN Module aborts the current transmission or reception of a message and enters the reset state. A reset request may be generated by an external reset, by the CPU, or by the CAN Module itself. The RR bit can only be cleared by the CPU. After the RR bit has been cleared, the CAN Module will begin normal operation in one of two ways. If RR was generated by an external reset or by the CPU, then the CAN Module starts normal operation after the first occurrence of 11 recessive bits. If, however, the RR was generated by the CAN Module due to the 146
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DESIGN OF A CUSTOM ASIC INCORPORATI
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ABSTRACT The vast majority of today
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LIST OF ABBREVIATIONS AND SYMBOLS A
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ISO International Organization for
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SI Serial In SO Serial Out SOF Star
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ACKNOWLEDGEMENTS I would like to ex
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2.4 Types of Devices...............
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4.3.5 Communication Speed Different
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5.3.21.1 Synchronization Test (test
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5.3 Resource Utilization...........
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LIST OF FIGURES 2.1 1 - Wire® Netw
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4.12 Read-Data Time Slot...........
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6.4 DS1996 Address Registers ......
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manufacturing process. Structured o
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describes the 1 - Wire® and CAN co
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2.2 1 - Wire® Overview The basis o
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All 1 - Wire® masters described in
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attachments, microcontroller with b
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Figure 2.3 Bidirectional port pin w
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2.3.3 Synthesizable 1 - Wire® Bus
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Figure 2.7 UART/RS232 Serial Port I
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hardware. Through control registers
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Table 2.2 1 - Wire® Bus Operations
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2.3.6 1 - Wire® Search Algorithm F
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detected. This ‘read two bits’
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in Figure 2.15. Alternatively, the
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of the bit, then write the desired
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2.4.2 Device Functions and Typical
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and development (R&D) investments b
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2.5 Network Types and Precedents As
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2.5.2 1 - Wire® Network Topologies
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2.5.3 1 - Wire® Network Limitation
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with a single selected slave. If an
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user group was founded in March of
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protocol on multiple media for maxi
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ecessive bit and the monitored stat
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specification: Start-Of-Frame, Arbi
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Cyclic Redundancy Check (CRC) Field
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Arbitration FieldThe Arbitration Fi
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SOF SOF Bit 28 Bit 27 Arbitration f
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Afterwards it starts transmitting s
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Figure 3.9 Structure of the Interfr
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error occurs, an Error Frame is gen
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Table 3.4 Error Flag Output Timing
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3.5.2 Error-Passive A node becomes
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where tNBT is the Nominal Bit Time
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Figure 3.12 Propagation Delay Betwe
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3.6.4 Synchronization t t t t (3.
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opposite value is inserted into the
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many systems, the bus length will b
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CHAPTER 4 THE CHALLENGES OF INTERFA
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In June 2004, Maxim Integrated Prod
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Wearable sensor technology is a new
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In traditional bus architectures, o
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Figure 4.3 Centralized arbiter with
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For the initial prototype design pr
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the ID of 31 transmits a ‘0’ (d
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Recently, a technique has been prop
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procedure, then the address claim p
Page 119 and 120: paradigms are prevalent in the desi
Page 121 and 122: systems possess a higher flexibilit
Page 123 and 124: fixed identifier and hence a fixed
Page 125 and 126: 348sm Cm 47 8 smbit 11-bit hea
Page 127 and 128: est-case latency occurs when the bu
Page 129 and 130: to break the 1 - Wire® network int
Page 131 and 132: ow, is most critical for power deli
Page 133 and 134: computations have device-specific p
Page 135 and 136: Table 4.7 Example results with N 2
Page 137 and 138: 4.3.5 Communication Speed Different
Page 139 and 140: anging” a port pin on a microproc
Page 141 and 142: From Figure 5.1, the block I/O pins
Page 143 and 144: 5.2.2 Command Register In addition
Page 145 and 146: specifies the selected bit value to
Page 147 and 148: with i > m. This process is repeate
Page 149 and 150: Figure 5.6 Interrupt Register. OW_
Page 151 and 152: the INTR pin will be pulled high si
Page 153 and 154: master reset occurs. Table 5.2 show
Page 155 and 156: EN_FOW: Enable Force One Wire. Sett
Page 157 and 158: READ_ROM - Used to read the 64-bit
Page 159 and 160: 5.2.8.1 Single Search ROM (single_s
Page 161 and 162: 5.2.8.3 Scratchpad Memory (scratchp
Page 163 and 164: 5.2.8.4 Command Recognition (cmd_re
Page 165 and 166: TBF - The Transmit Buffer provides
Page 167 and 168: compensate for the propagation dela
Page 169: Figure 5.15 CAN Module memory map [
Page 173 and 174: COMP-SEL: Comparator Select. When t
Page 175 and 176: Figure 5.18 CAN Status Register. B
Page 177 and 178: that buffer is given to the CPU and
Page 179 and 180: Acceptance Mask Registers (accepted
Page 181 and 182: SJW1, SJW0: Synchronization Jump Wi
Page 183 and 184: TSEG22 - TSEG10: Time Segment Bits.
Page 185 and 186: The transmit clock (ttxclk) is used
Page 187 and 188: 5.3.13 CAN Module Transmit Buffer I
Page 189 and 190: Figure 5.28 CAN Transmit Data Segme
Page 191 and 192: 5.3.20 CAN Node Overview As stated
Page 193 and 194: Read Digital InputsRead the value o
Page 195 and 196: the clock high time is either 5 µs
Page 197 and 198: Yes Perform A/D Conversion on AN0 W
Page 199 and 200: and GP2 and GP5 as outputs. With th
Page 201 and 202: external INT pin, and then branches
Page 203 and 204: Read MCP2515 Rx Buffer for Digital
Page 205 and 206: When a valid message is received, t
Page 207 and 208: Table 5.19 Resource Utilization. Re
Page 209 and 210: For this test, only one CAN node wa
Page 211 and 212: an Error Frame to be generated. Aft
Page 213 and 214: messages, acknowledge messages, or
Page 215 and 216: 5.3.21.4 Send Basic Frame Test (sen
Page 217 and 218: going from one node to 30 nodes (se
Page 219 and 220: Table 6.1 Resource Utilization. Rev
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6.2.1 Test Verification and Overvie
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has read access to this register. T
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system configuration used for this
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or not depends on the number of rec
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6.4. There are two receiving CAN no
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CHAPTER 7 CONCLUSIONS AND FUTURE WO
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a communication bus reset will occu
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For the synthesizable CAN Controlle
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additional CAN nodes were added to
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Fall-Through Stack A LOW level on t
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In conclusion, the prototype system
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REFERENCES [1] IBM ASIC Products Ap
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[22] “CAN - a brief tutorial for
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[44] Microchip MCP2515 - Stand-Alon
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[67] K. Tindell and A. Burns, “Gu
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[88] “Verilog - A Language Refere
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