DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...

Table 5.8 Control Registers [95 – 96].
Register Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Control (CCNTRL) 10h X SPD X OIE EIE TIE RIE RR
Command (CCOM) 11h RX0 RX1 COMP-SEL SLEEP COS RRB AT TR
Status (CSTAT) 12h BS ES TS RS TCS TBA DO RBS
Interrupt (CINT) 13h X X X WIF OIF EIF TIF RIF
Acceptance code (CACC) 14h AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
Acceptance mask (CACM) 15h AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
Bus timing 0 (CBT0) 16h SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0
Bus timing 1 (CBT1) 17h SAMP TSEG-22 TSEG-21 TSEG-20 TSEG-13 TSEG-12 TSEG-11 TSEG-10
Output Control (COCNTRL) 18h OCT-P1 OCT-N1 OCPOL1 OCT-P0 OCT-N0 OCPL0 OCM1 OCM0
Test Register 19h X X X X X X X X
Note: The acceptance code register, acceptance mask register, bus timing register 0, bus timing
register 1 and the output control register are only accessible when the RESET REQUEST
(RR) bit in the CAN control register (CCNTRL) is set. It is not foreseen that these
registers will be referenced again after the initial reset sequence [95].
5.3.3 CAN Module Control Register (CCNTRL)
The Control Register, shown in Figure 5.16, provides the local mask bits for the CAN
Module interrupts. In addition, it contains the Reset Request (RR) bit, which is set to disable the
CAN Module operation and allow access to the message filtering, bus timing and output
control registers [96]. This register may be read or written by the microprocessor; only the RR
bit is affected by the CAN Module.
Figure 5.16 CAN Control Register.
SPD: Speed Mode. When this bit is set to ‘1’, slow speed mode will be used for
resynchronization. Bus line transitions from both recessive to dominant and from
dominant to recessive will be used for resynchronization. When this bit is cleared, set to
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