DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...

CPU or external microcontroller and connects the CPU busses to the CAN busses. It also
generates internal control signals from internal CPU signals.
Figure 5.14 Controller Interface Logic Unit (CIL) [95 – 96].
The control lines are comprised of a reset input line and an interrupt line. In addition to
the control lines are the 8-bit multiplexed address/data bus lines. Together these lines, which are
tied back to the IML Unit of the CAN Controller Module, aid in the interpretation of
commands from the CPU, help control the allocation of the message buffers (both Tx and Rx),
and supply interrupt and status information to the CPU via the CIL.
5.3.1 Register Map and Address Allocation
The CAN Controller Module memory map is shown in Figure 5.15. There are three
main register blocks discussed here: control registers (10 bytes), transmit buffer (10 bytes), and
receive buffer (10 bytes). The individual registers in each of these blocks will be described in
the sections to follow.
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