DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...

e received may be lost. To reduce the requirements on the CPU, two receive buffers
(RBF0 and RBF1) are implemented. While one receive buffer is allocated to the CPU,
the BSP may write to the other buffer. RBF0 and RBF1 are each 10 bytes long and hold
the Identifier (1 byte), the Control Field (1 byte) and the Data Field (maximum length of
8 bytes). The BSP only writes into a receive buffer when the message being received or
transmitted has an Identifier which passes the Acceptance Filter.
BSP – This is a sequencer controlling the data stream between the Transmit and Receive
Buffers (parallel data) and the CAN (serial data). The BSP also controls the
Transceive Logic (TCL) and the Error Management Logic (EML) such that the processes
of reception, arbitration, transmission and error signaling are performed according to the
protocol and the bus rules. The BSP also provides signals to the IML indicating when a
Receive Buffer contains a valid message and when the Transmit Buffer is no longer
required after a successful transmission. The automatic retransmission of messages,
which have been corrupted by noise or other external conditions on the bus line, is
effectively handled by the BSP.
BTL – The Bit Timing Logic block monitors the CAN bus line using an input
comparator and handles the CAN bus line related bit timing. The BTL synchronizes
on a recessive-to-dominant bus line transition at the Start of Frame (hard
synchronization), and resynchronizes on further transitions during reception of a frame
(soft synchronization). A programmable control bit in the CPU determines which edges
are used for resynchronization. The BTL also provides programmable time segments to
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