DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...

5.3 CAN (Controller Area Network) FPGA Implementation
For the FPGA implementation of the CAN Controller, the Bosch VHDL Reference System
was used as a guide and verification test tool. Some of the features incorporated into the design
are:
Implementation of the Basic CAN specification.
Receiving and transmitting of 11 and 29-bit identifiers.
Programmable baud rate prescaler (up to 1/256).
Up to 1 Mbit/sec speeds of operation.
Message based filtering and addressing.
Non-Destructive bitwise arbitration (CSMA/CA).
Readable Error Counters.
Maskable Error and Status Interrupts.
Figure 5.13 contains a block diagram of a CAN Controller showing only the major
blocks. It is designed to be memory-mapped into any system and is based on the Motorola
CAN (MCAN) Module [95 – 97]. All hardware modules necessary to implement the CAN
Transfer Layer (Bit Stream Processor and Bit Timing Logic) are included, representing the
kernel of the CAN bus protocol as defined by Bosch GmbH, the originators of the CAN
specification. From Figure 5.13, the hardware modules are defined as follows:
IML – The Interface Management Logic unit interprets the commands from the CPU,
controls allocation of both transmit and receive buffers, and supplies interrupts and status
information to the CPU via the Controller Interface Logic (CIL) Unit (See Figure 5.14).
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