DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...

5.2.8.3 Scratchpad Memory (scratchpad_integrity) Test
The scratchpad memory in a 1 – Wire® slave device is written to and read from using the
WRITE_SP (0x0Fh) and READ_SP (0xAAh) commands. The eight bytes of data being written
are random and are stored at the bus functional model (i.e. Verilog® code software) while also
being written to the one_wm block and sent across to the 1 – Wire® slave device. The data
written to the slave device is then read back and compared to the previously stored value in the
bus functional model. This test also verifies proper operation of the device addressing
instruction SKIP_ROM (0xCC).
For the eight bytes of random data the Verilog® statistical function $random() was used.
The $random() function returns a new 32-bit random number each time it is called. The return
type is a signed integer. An optional seed_expression can be used to control the random number
generation and must be a signed integer value, a register, or a time variable. Additionally the
modulus operator % can be used to restrict the return value (i.e. for b > 0,
$random(seed_expression) %b will restrict the random number returned to (-b + 1) : (b – 1) [88].
For this test only a single 1 – Wire® slave exists on the 1 – Wire® network. Figure 5.12
shows the setup configuration used to conduct this test. Just like the previous test cases, any
configurable FPGA I/O pin on the Altera DE2 Development and Education board can serve as
the 1 – Wire Master I/O pin. Only 1 – Wire® devices having an internal scratchpad area in
memory were used to conduct this test (See Table 5.6). As was done in the previous tests, the 1
– Wire® devices listed in Table 5.6 were hot swapped during execution of the test to check for
data integrity and failures in the design of the 1 – Wire® network. The test results, summarized
in Table 5.6, verified that the correct single ROM_ID was found by the Search ROM Accelerator
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