DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...

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5.3.6 CAN Module Interrupt Register (CINT) ............................................................152 5.3.7 CAN Module Acceptance Code Register (CACC) .............................................153 5.3.8 CAN Module Acceptance Mask Register (CACM) ...........................................154 5.3.9 CAN Module Bus Timing Register 0 (CBT0) ....................................................155 5.3.10 CAN Module Bus Timing Register 1 (CBT1) ..................................................157 5.3.11 CAN Module Output Control Register (COCNTRL) .......................................159 5.3.12 CAN Module Transmit Buffer Registers Overview .........................................161 5.3.13 CAN Module Transmit Buffer Identifier Register (TBI)..................................162 5.3.14 CAN Module Remote Transmission Request/Data Length Code Register (TRTDL) ..........................................................................................................................162 5.3.15 CAN Module Transmit Data Segment Registers (TDS) 1 – 8 ..........................163 5.3.16 CAN Module Receive Buffer Registers Overview ...........................................164 5.3.17 CAN Module Receive Buffer Identifier Register (RBI) ...................................165 5.3.18 CAN Module Remote Transmission Request/Data Length Code Register (RRTDL) ..........................................................................................................................165 5.3.19 CAN Module Receive Data Segment Registers (RDS) 1 – 8 ...........................165 5.3.20 CAN Node Overview ........................................................................................166 5.3.20.1 Firmware Description ..................................................................................171 5.3.20.2 PIC® MCU Initialization .............................................................................173 5.3.20.3 MCP2515 Initialization ................................................................................175 5.3.20.4 Interrupt Service Routine .............................................................................175 5.3.21 Verification of CAN Module ............................................................................181 xv
5.3.21.1 Synchronization Test (test_synchronization) ...............................................182 5.3.21.2 Bus-Off Test (bus_off_test) .........................................................................183 5.3.21.3 Error Test (error_test) ..................................................................................185 5.3.21.4 Send Basic Frame Test (send_frame_basic) ................................................190 5.3.21.5 Send Extended Frame Test (send_frame_extended) ....................................191 6 1 – WIRE® <strong>AND</strong> CAN COMBINED SYSTEM PROTOTYPE IMPLEMENTATION ....193 6.1 Overview of Integrated System .......................................................................................193 6.2 Verification of Combined Prototype System ...................................................................195 6.2.1 Test Verification and Overview ..............................................................................196 6.2.1.1 DS1996 Addressing and Memory Layout .....................................................197 6.2.1.2 Test Results – Transferring CAN data bytes to 1 – Wire® devices ..........199 6.2.1.3 Test Results – 1 – Wire® Master requests data from CAN nodes ............201 7 CONCLUSIONS <strong>AND</strong> FUTURE WORK ...............................................................................206 REFERENCES ............................................................................................................................218 xvi
Page 1 and 2: DESIGN OF A CUSTOM ASIC INCORPORATI
Page 3 and 4: ABSTRACT The vast majority of today
Page 5 and 6: LIST OF ABBREVIATIONS AND SYMBOLS A
Page 7 and 8: ISO International Organization for
Page 9 and 10: SI Serial In SO Serial Out SOF Star
Page 11 and 12: ACKNOWLEDGEMENTS I would like to ex
Page 13 and 14: 2.4 Types of Devices...............
Page 15: 4.3.5 Communication Speed Different
Page 19 and 20: 5.3 Resource Utilization...........
Page 21 and 22: LIST OF FIGURES 2.1 1 - Wire® Netw
Page 23 and 24: 4.12 Read-Data Time Slot...........
Page 25 and 26: 6.4 DS1996 Address Registers ......
Page 27 and 28: manufacturing process. Structured o
Page 29 and 30: describes the 1 - Wire® and CAN co
Page 31 and 32: 2.2 1 - Wire® Overview The basis o
Page 33 and 34: All 1 - Wire® masters described in
Page 35 and 36: attachments, microcontroller with b
Page 37 and 38: Figure 2.3 Bidirectional port pin w
Page 39 and 40: 2.3.3 Synthesizable 1 - Wire® Bus
Page 41 and 42: Figure 2.7 UART/RS232 Serial Port I
Page 43 and 44: hardware. Through control registers
Page 45 and 46: Table 2.2 1 - Wire® Bus Operations
Page 47 and 48: 2.3.6 1 - Wire® Search Algorithm F
Page 49 and 50: detected. This ‘read two bits’
Page 51 and 52: in Figure 2.15. Alternatively, the
Page 53 and 54: of the bit, then write the desired
Page 55 and 56: 2.4.2 Device Functions and Typical
Page 57 and 58: and development (R&D) investments b
Page 59 and 60: 2.5 Network Types and Precedents As
Page 61 and 62: 2.5.2 1 - Wire® Network Topologies
Page 63 and 64: 2.5.3 1 - Wire® Network Limitation
Page 65 and 66: with a single selected slave. If an
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user group was founded in March of
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protocol on multiple media for maxi
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ecessive bit and the monitored stat
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specification: Start-Of-Frame, Arbi
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Cyclic Redundancy Check (CRC) Field
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Arbitration FieldThe Arbitration Fi
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SOF SOF Bit 28 Bit 27 Arbitration f
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Afterwards it starts transmitting s
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Figure 3.9 Structure of the Interfr
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error occurs, an Error Frame is gen
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Table 3.4 Error Flag Output Timing
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3.5.2 Error-Passive A node becomes
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where tNBT is the Nominal Bit Time
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Figure 3.12 Propagation Delay Betwe
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3.6.4 Synchronization t t t t (3.
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opposite value is inserted into the
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many systems, the bus length will b
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CHAPTER 4 THE CHALLENGES OF INTERFA
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In June 2004, Maxim Integrated Prod
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Wearable sensor technology is a new
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In traditional bus architectures, o
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Figure 4.3 Centralized arbiter with
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For the initial prototype design pr
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the ID of 31 transmits a ‘0’ (d
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Recently, a technique has been prop
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procedure, then the address claim p
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paradigms are prevalent in the desi
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systems possess a higher flexibilit
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fixed identifier and hence a fixed
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348sm Cm 47 8 smbit 11-bit hea
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est-case latency occurs when the bu
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to break the 1 - Wire® network int
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ow, is most critical for power deli
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computations have device-specific p
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Table 4.7 Example results with N 2
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4.3.5 Communication Speed Different
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anging” a port pin on a microproc
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From Figure 5.1, the block I/O pins
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5.2.2 Command Register In addition
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specifies the selected bit value to
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with i > m. This process is repeate
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Figure 5.6 Interrupt Register. OW_
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the INTR pin will be pulled high si
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master reset occurs. Table 5.2 show
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EN_FOW: Enable Force One Wire. Sett
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READ_ROM - Used to read the 64-bit
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5.2.8.1 Single Search ROM (single_s
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5.2.8.3 Scratchpad Memory (scratchp
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5.2.8.4 Command Recognition (cmd_re
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TBF - The Transmit Buffer provides
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compensate for the propagation dela
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Figure 5.15 CAN Module memory map [
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‘0’, fast speed mode will be us
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COMP-SEL: Comparator Select. When t
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Figure 5.18 CAN Status Register. B
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that buffer is given to the CPU and
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Acceptance Mask Registers (accepted
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SJW1, SJW0: Synchronization Jump Wi
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TSEG22 - TSEG10: Time Segment Bits.
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The transmit clock (ttxclk) is used
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5.3.13 CAN Module Transmit Buffer I
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Figure 5.28 CAN Transmit Data Segme
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5.3.20 CAN Node Overview As stated
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Read Digital InputsRead the value o
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the clock high time is either 5 µs
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Yes Perform A/D Conversion on AN0 W
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and GP2 and GP5 as outputs. With th
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external INT pin, and then branches
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Read MCP2515 Rx Buffer for Digital
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When a valid message is received, t
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Table 5.19 Resource Utilization. Re
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For this test, only one CAN node wa
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an Error Frame to be generated. Aft
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messages, acknowledge messages, or
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5.3.21.4 Send Basic Frame Test (sen
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going from one node to 30 nodes (se
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Table 6.1 Resource Utilization. Rev
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6.2.1 Test Verification and Overvie
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has read access to this register. T
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system configuration used for this
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or not depends on the number of rec
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6.4. There are two receiving CAN no
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CHAPTER 7 CONCLUSIONS AND FUTURE WO
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a communication bus reset will occu
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For the synthesizable CAN Controlle
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additional CAN nodes were added to
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Fall-Through Stack A LOW level on t
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In conclusion, the prototype system
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REFERENCES [1] IBM ASIC Products Ap
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[22] “CAN - a brief tutorial for
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[44] Microchip MCP2515 - Stand-Alon
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[67] K. Tindell and A. Burns, “Gu
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[88] “Verilog - A Language Refere
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